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Forum - Thread List
  • Discussion

    SIMULATION PROBLEM IN SPECRES OF CADENCE Locked

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    Started over 18 years ago
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  • Discussion

    Verisity Register eVC Locked

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    4 replies
    Latest over 18 years ago
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  • Discussion

    Equivalent of AHB eVC in system verilog Locked

    13738 views
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    Latest over 18 years ago
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  • Discussion

    Skill function for back-annotation Locked

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    10 replies
    Latest over 18 years ago
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  • Discussion

    Height Constraints Locked

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    7 replies
    Latest over 18 years ago
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  • Discussion

    New to RTL Compiler Locked

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    2 replies
    Latest over 18 years ago
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  • Discussion

    About 'setEcoMode' command & How to add self-defined menus for SOC Encounter Locked

    6183 views
    2 replies
    Latest over 18 years ago
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  • Discussion

    Search Path and Packages, Interface, etc. Locked

    14925 views
    4 replies
    Latest over 18 years ago
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  • Discussion

    Should you have pads on the power and gnd layers in stackup Locked

    14146 views
    4 replies
    Latest over 18 years ago
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  • Discussion

    HD Audio eVC/uVC Locked

    407 views
    0 replies
    Started over 18 years ago
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  • Discussion

    IPCM question? Locked

    14020 views
    3 replies
    Latest over 18 years ago
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  • Discussion

    usefulskew,drivercell Locked

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    Started over 18 years ago
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  • Discussion

    usefulskew,drivercell Locked

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    0 replies
    Started over 18 years ago
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  • Discussion

    Can I force or probe a signal in vhdl module from verilog top testbench? Locked

    17526 views
    6 replies
    Latest over 18 years ago
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  • Discussion

    How to tackle 'Aborted' properties. Locked

    6170 views
    3 replies
    Latest over 18 years ago
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