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Forum - Thread List
  • Discussion

    sweeping transistor number of fingers in a simulation

    1907 views
    2 replies
    Latest 5 months ago
    by TommasoF
  • Discussion

    Need a script to remove extra metal overhang after vias which we generally chop and delete manually

    3274 views
    1 reply
    Latest 5 months ago
    by rajeshcad
  • Discussion

    Ring oscillator separation gate delay and interconnect delay Locked

    2136 views
    0 replies
    Started 5 months ago
    by SL202509028216
  • Not Answered

    Orcad capture 22 title block auto population 0

    1122 views
    2 replies
    Latest 5 months ago
    by MR20250829531
  • Discussion

    xrun: *F,SROOTE: Cannot find the Spectre installation

    962 views
    3 replies
    Latest 5 months ago
    by Andrew Beckett
  • Discussion

    use DC sweep variable to set another variable

    1596 views
    2 replies
    Latest 5 months ago
    by Darrell L
  • Discussion

    Attach load to a pin for AMS verification Locked

    1811 views
    0 replies
    Started 5 months ago
    by PedroC
  • Discussion

    Code coverage syntax for scripting tcl exclusion file

    2811 views
    1 reply
    Latest 5 months ago
    by StephenH
  • Discussion

    automate cadence design to avoid time consuming steps for simulation using python subprocess module.

    1311 views
    0 replies
    Started 5 months ago
    by AP202507218251
  • Discussion

    ERROR (NVN-13010): Cell rupolym is not defined while running Pegasus LVS

    1866 views
    3 replies
    Latest 5 months ago
    by Andrew Beckett
  • Discussion

    CAF Resistance and SIR Testing: Preventing Hidden PCB Failures Through Smarter Design & Process Control

    3489 views
    4 replies
    Latest 5 months ago
    by KD202502275710
  • Discussion

    Community ideas

    1143 views
    2 replies
    Latest 5 months ago
    by KD202502275710
  • Not Answered

    Dynamically update/reload the CIS Configuration in a running OrCAD Instance 0

    1066 views
    2 replies
    Latest 5 months ago
    by KD202502275710
  • Discussion

    Discussion on Poly-Endcap in CMOS Layout

    2825 views
    1 reply
    Latest 5 months ago
    by yogeshjaiswalCAD
  • Discussion

    All pins on schematics unconnected to their attached wires when importing EDIF from Siemens,

    2244 views
    4 replies
    Latest 5 months ago
    by Andrew Beckett
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