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Forum - Thread List
  • Discussion

    Why pin object is converted to shape in Abstract generator Locked

    10148 views
    1 reply
    Latest over 4 years ago
    by Andrew Beckett
  • Discussion

    How to find "file signature" of design files in Cadence Virtuoso (schematics, layouts, symbols, etc.) Locked

    3521 views
    6 replies
    Latest over 4 years ago
    by Andrew Beckett
  • Discussion

    Weird behavior when using drGetWaveformYVec and drGetElem with a logic signal Locked

    10675 views
    1 reply
    Latest over 4 years ago
    by Andrew Beckett
  • Discussion

    padstack question Locked

    9691 views
    1 reply
    Latest over 4 years ago
    by steve
  • Discussion

    IMC exception on opening .ucm from xrun coverage generation Locked

    15769 views
    1 reply
    Latest over 4 years ago
    by StephenH
  • Discussion

    Transient simulation termination by VerilogA model Locked

    12998 views
    4 replies
    Latest over 4 years ago
    by Senan
  • Discussion

    How to convert Shape to Cline?

    10370 views
    0 replies
    Started over 4 years ago
    by ichliebedich
  • Discussion

    can I just place one cap from Vcc+ to Vcc- on the adaptor board to cover both IC's? Locked

    971 views
    0 replies
    Started over 4 years ago
    by kaylee
  • Discussion

    Utilising a Form 'Help' Callback Locked

    2152 views
    2 replies
    Latest over 4 years ago
    by kdolan
  • Discussion

    Verilog Error Locked

    13121 views
    1 reply
    Latest over 4 years ago
    by Andrew Beckett
  • Not Answered

    pnR problem 0

    11099 views
    0 replies
    Started over 4 years ago
    by soodswar
  • Discussion

    Creating Logical only part with fully named variations Locked

    9036 views
    0 replies
    Started over 4 years ago
    by Troy Wilson
  • Discussion

    Create a opening in a existing copper pour.

    13500 views
    5 replies
    Latest over 4 years ago
    by OLY29
  • Discussion

    How do I make Denali AXI VIP print summary of the bursts it got/sent during a test? Locked

    1714 views
    0 replies
    Started over 4 years ago
    by avidanefody
  • Discussion

    OrCAD CIS multi manufacturer relation table. Locked

    9305 views
    0 replies
    Started over 4 years ago
    by Amitp
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