• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Forum - Thread List
  • Discussion

    Nested for loop Locked

    16668 views
    9 replies
    Latest over 5 years ago
    by Leonardo Vinci
  • Discussion

    Resistor DIP 4 A-D from Discrete library Locked

    12902 views
    1 reply
    Latest over 5 years ago
    by AvengerThanos
  • Discussion

    Calculating timing delay from routed channel length

    13594 views
    0 replies
    Started over 5 years ago
    by dontknowwhy
  • Discussion

    How do make the clock 25% duty cycle with jitter capability Locked

    16626 views
    4 replies
    Latest over 5 years ago
    by Andrew Beckett
  • Discussion

    is there a way to use axlDBCreateShape to create a Dynamic shape attached to a symbol?

    10097 views
    2 replies
    Latest over 5 years ago
    by HJerry
  • Discussion

    install Cadence IC 615 on CentOS 6.2: configure status failed Locked

    19136 views
    5 replies
    Latest over 5 years ago
    by PankajPal
  • Discussion

    Bus routing in Allegro PCB Designer

    15426 views
    5 replies
    Latest over 5 years ago
    by RFinley
  • Discussion

    Looking for ADVFC32 SPICE Model

    13015 views
    0 replies
    Started over 5 years ago
    by opelininr
  • Discussion

    How to pass the file name as a variable to vsource as PWL type Locked

    16873 views
    4 replies
    Latest over 5 years ago
    by oljd
  • Discussion

    Sparam resonance tuning problem Locked

    14614 views
    1 reply
    Latest over 5 years ago
    by Andrew Beckett
  • Discussion

    Lint Manager Outputs Locked

    14139 views
    3 replies
    Latest over 5 years ago
    by SrBraj
  • Not Answered

    How to use POWERDC .SUBCKT in PSPICE simulation 0

    13225 views
    2 replies
    Latest over 5 years ago
    by effedipi
  • Discussion

    How to generate a clock signal with random noise in Cadence Spectre? Locked

    28441 views
    3 replies
    Latest over 5 years ago
    by Andrew Beckett
  • Discussion

    Method to scale up or down lots of resistor/capacitor value together Locked

    2227 views
    1 reply
    Latest over 5 years ago
    by henker
  • Discussion

    Mixed-signal CDL netlist export Locked

    14808 views
    1 reply
    Latest over 5 years ago
    by Andrew Beckett
<>

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information