• Discussion

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  7 replies
  Latest over 6 years ago
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• Discussion

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  2 replies
  Latest over 6 years ago
  by VLSI lab IITB
• Discussion

  The veriloga code when simulted in cadence shows the following error though all the syntax and identifiers match the accellera. Thanks in advance. Locked

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  4 replies
  Latest over 6 years ago
  by Avieee
• Discussion

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• Discussion

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• Discussion

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• Discussion

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  Latest over 6 years ago
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• Discussion

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  1 reply
  Latest over 6 years ago
  by johnthanchau
• Discussion

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  1 reply
  Latest over 6 years ago
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• Discussion

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• Discussion

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• Discussion

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• Discussion

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• Discussion

  Weird voltage level in verilogA simulation Locked

  15050 views
  2 replies
  Latest over 6 years ago
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• Discussion

  Signal/Power Integrity Problem Locked

  496 views
  0 replies
  Started over 6 years ago
  by HirosakiOnda