• Discussion

  Schematic Extraction of Standard Cells of TSMC 40nm and AMS Locked

  16204 views
  1 reply
  Latest over 7 years ago
  by Saloni Chhabra
• Discussion

  how to convert text string to integer in VerilogA? Locked

  25971 views
  12 replies
  Latest over 7 years ago
  by DavidLou
• Discussion

  Loading the DFA Table using Skill

  11487 views
  5 replies
  Latest over 7 years ago
  by DavidJHutchins
• Discussion

  Replace footprint on PCB Editor

  13884 views
  1 reply
  Latest over 7 years ago
  by oldmouldy
• Discussion

  possible to instantiate Verilog module in VerilogA? Locked

  21017 views
  6 replies
  Latest over 7 years ago
  by DavidLou
• Discussion

  Load pull - Differential Locked

  4866 views
  2 replies
  Latest over 7 years ago
  by Alex Tiler
• Discussion

  I want to learn PCB design Locked

  14650 views
  1 reply
  Latest over 7 years ago
  by excellon1
• Discussion

  Can ViVa display internal variables of VerilogA model? Locked

  15685 views
  2 replies
  Latest over 7 years ago
  by DavidLou
• Discussion

  layout XL extract cellviews in hierarchy? Locked

  14484 views
  0 replies
  Started over 7 years ago
  by yeh1
• Discussion

  removing repetitions from list with same elements but in reverse order Locked

  15387 views
  4 replies
  Latest over 7 years ago
  by RAGHU2634
• Discussion

  Converting Waveform to list Locked

  18106 views
  5 replies
  Latest over 7 years ago
  by Andrew Beckett
• Discussion

  import spice net list created from calibre lvs tool Locked

  15410 views
  1 reply
  Latest over 7 years ago
  by Andrew Beckett
• Discussion

  long time ocean simulation w/o saving any waveform database Locked

  3747 views
  8 replies
  Latest over 7 years ago
  by DavidLou
• Discussion

  Time in Simvision's Expression calculator Locked

  9690 views
  5 replies
  Latest over 7 years ago
  by evancox10
• Discussion

  performance: constraints list of lists Locked

  13801 views
  0 replies
  Started over 7 years ago
  by Gabv