encounter -error while loading design

Hi,

I had this for my design as well for a certain cell.

 Technically, you should have the library vendor fix this LEF. You could fix it yourself if you feel confident doing such things. However, since an OBS (obstruction) is not a manufacturable shape, you can ignore this offgrid warning. If you ever get an offgrid warning about pins, nets/wires, cell placements, etc. then those MUST be fixed.

 "Offgrid" means off the manufacturing grid. The manufacturing grid is the smallest resolution that the manufacturing equipment is capable of. So the edges of all shapes must align to this grid. The grid can be found in the tech LEF (MANUFACTURINGGRID 0.005 ;), but to double-check that the LEF is correct, I would consult the design rule manual.

Obstruction layers, also called blockages, are used in LEF files as an abstraction of more detailed metal. For example, the actual layout of an AND cell has lots of shapes, but in a place and route tool, you just need to know the size of the AND cell, the shape and locations of the pins, and the locations you CAN'T put routing metal - that's where the obstructions come in. Instead of the LEFs having every little detail (file would be huge and runtimes long), it uses the OBS layers. (Not sure if I explained that very well.)

Since the manufacturing grid is stated in the LEF, it is very unlikely that you would get any pins/cells/nets/wires offgrid, but it can happen. For example, you may hand-route something and turn off "snap to grid". If something like that does happen, it's usually very easy to move the wire or the cell, etc. Verify Geometry will flag offgrid violations; make sure you run that.

 Hope that helps.

 Hi Gops,

 The placement grid is not the same as the manufacturing grid. The placement grid is the smallest step size of the std cell rows. If you look at your tech LEF at the definition for the std cell row, the first number in the SIZE line tells you the placement grid. That means that your smallest filler cell should be that size. On the "All Colors" form, under the "View Only" tab, you can turn on the placement grid. You may have to zoom in really close to see it. In the Design->Preferences menu, on the Floorplan tab, there are settings for which grid to snap to for various floorplan objects. The defaults are good settings.

There are also routing grids. These are the pitches for each metal layer as defined in the LEF. You can turn these on from the same place you turned on the placement grid. Also, when editing wires (hit "e" to make the Edit Route form come up), look at the "Snap" tab. You can turn on or off snapping to routing grids, also called routing tracks. Even if you turn these off, the wires should still be legal on the manufacturing grid.

Hope that clears up the subject of grids a little bit!

- Kari 

dear all,

I got the same **ERROR warning

I just started to used cadence for digital implementation in this month.

I made simple shift register and follow the orders on some tutorial. It was finish and error-free until [ADD FILLER] process, write lef file [using letOut command] and save my design. But when I try to reload my design, it generate:

**ERROR: (SOCLF-82):    The x coordinate value 2.7700
in pin 'Y' in macro 'ROHM18AND2P005' is not on the manufacturing grid.
It's likely to result in placement/routing that can not be manufactured.

I thought I can fixed the problem with start all over again from synthesis process, but I found that whatever setting that I used there always result [Violating Paths: not-0]

Is that any connection between 2 cases?

 Hi Akari,

 What is your manufacturing grid? This could be a real problem, but could be easily fixed by moving the macro. Need more details to know for sure.

 - Kari

 Hi,

I see some filler cells which have metal pins offGrid. When I run verifyGeometry with the option -offRGrid, It flags some violations which says some filler cells have pins which do not cover at least one grid point on the routing grid.

 Is this possible ?

 Aditya