Cadence/Samsung Automotive Reference Flow

8 Apr 2021 • 6 minute read

Today, Cadence and Samsung announced the availability of an Automotive Reference Flow for Samsung Foundry's 14LPU process technology. In the press release back in 2016 when the process was first announced, Samsung said:

Samsung’s fourth-generation 14nm process technology, 14LPU, delivers higher performance at the same power and design rules compared to its third-generation 14nm process (14LPC). 14LPU will be optimally suited for high-performance and compute-intensive applications.

And automotive.

For more details on Samsung's processes, see my post Samsung Process Roadmaps.

Late last year Samsung Foundry held their SAFE symposium. SAFE stands for Samsung Advanced Foundry Ecosystem. Actually, Samsung is such a large company with such a broad product line that it can't even keep an acronym unique—SAFE also stands for SAmsung For Enterprise, "a line of smartphones and tablets manufactured to meet specific enterprise management and security criteria". Well, here at Breakfast Bytes, we're obviously most interested in the first one of those.

At SAFE 2020, Cadence's Rob Knoth presented the flow.

Cadence/Samsung Automotive Reference Flow

The flow was demonstrated using a Tensilica core, the ConnX B10 DSP. This core is not limited to automotive, and it is also widely used in 5G basestations. In automotive, it is mainly used for implementing radar, lidar, and V2X communication. For more details on this see my post Implementing Automotive Radar on Tensilica Processors. For more information on the ConnX family of cores, see my post Tensilica ConnX B20 for 5G, and Automotive Radar/Lidar.

But for automotive, it is not good enough to be good enough—certification of compliance is a requirement. So the ConnX B10 core was previously certified in accordance with the automotive ISO 26262:2018 functional safety standard, making it the ideal choice for customers considering the Samsung 14LPU platform for safety-critical applications. The certification confirmed that ConnX B10 DSP is compliant with ASIL-B random hardware faults and ASIL-D systematic faults, which is critical for autonomous driving, advanced driver assistance systems (ADAS), and other automotive applications. For more on ISO 26262, see my posts:

The basis of the flow was Genus, Innovus, and the signoff engines. Together, this is known as Digital Full Flow. For more details on this, see my post Digital Full Flow for 5/7nm (and yes, the automotive flow is in 14nm but most of what is in this post applies). My post Use Your Imagination to Get Smaller, Faster Chips is about implementing a GPU, but again most of it is relevant to any large automotive design, too.

Quality, Reliability, and Safety

Of course, for any SoC, the Cadence Digital Full Flow delivers first-pass silicon and optimal power, performance, and area (PPA). But for automotive, it needs to deliver quality, reliability, and safety.

Quality means that a design meets its specification at the start of its life, with a target of 0 defective parts per million (DPPM). This involves various aspects of design, but a major focus is on test, ensuring that no bad parts "escape", meaning that they pass manufacturing test but fail in the vehicle. For more on this, see my posts Modus DFT Has Been ISO 26262 Certified by TÜV-SÜD, and Cell-Aware Test: Research Cooperation Between Cadence, imec, and TU Eindhoven...Now Shipping in Modus DFT Software Solution.

Reliability means that a design continues to meet its specification throughout the lifetime of the chip. This is measured in FITS, "failures in time", meaning how many failures occur in a billion hours of operation. Achieving good reliability (low FITS) requires considering aging of the transistors over the extended lifetime required for automotive (compared to, say, smartphones). For more on this, see my posts Automotive Reliability: The Bathtub Curve and Legato: Making the Bathtub Wider and Deeper. The focus of aging has to be on the analog parts of the SoC, since well over 80% of automotive chip failures are from the analog portion of the design. Digital design is inherently more reliable, since a voltage can change a lot before it flips from 0 to 1.

Safety covers the case when there is a failure in the chip. The goal is to "fail safely". For example, if your airbag controller detects a fault, you want two things to happen: first, it doesn't deploy the airbag accidentally, and second that it turns on a dashboard light—or increasingly these days puts an icon on your display screen—so that you take it to the dealer and get it fixed. This requires FMEDA (failure modes, effects, and diagnostic analysis), which means working out in advance all the failure modes and how to handle them. There are also safety architectures such as triple-redundant-voting flops: if a bit flips in a register, perhaps by a SEE (single event effect) it gets outvoted since two duplicate registers will have the correct value. For more on this, see my posts Make Sure Your Car Doesn't Break Too Often...When It Does, Make Sure You Catch It and CDNDrive: Automotive Functional Safety. Also Accellera Functional Safety.

Details of the Demonstration Project

Goals:

Meaningful automotive design – the Tensilica ConnX B10 DSP
SW diagnostics, enhanced memory ECC for automotive, Triple Voting Flops (TVF)
Targeted at automotive process node, Samsung's LN14LPU
Focus on implementation and signoff
Automotive design implementation flow for functional safety and reliability with Genus/Innovus/Voltus/Tempus solutions
ISO 26262 targeting ASIL B
AEC-Q100 Grade 1 (150℃ junction temperature)

Design achieved:

B10 DSP, Extended SP-VFPU, VTCM3-based ECC memories
AEC-A100 Grade 1
Targeted ASIL-B implementation
~1.5M instances, Utilization 65%

Technology library:

Samsung LN14LPU PDK
Track and CPP: 9 track, 84CPP
Metal stack: 10M_3Mx_4Cx_2Kx_1Gx_LB
Arm LN14LPU DKIT
Standard cell version: r0p0
Memory compiler version: r0p0

Triple Voting Flops

FMEDA identifies which flops need to be triple redundant to meet ISO 26262 ASIL B compliance. These are inserted by Genus/Innovus, and then Conformal is used to verify that the functionality of the design has not been changed by the redundant flops. In the diagram below, you can see the redundant flops, which are widely separated so that they are as independent as possible and unlikely to be affected by the same problem.

Design for Manufacturing

DFM is integrated into the flow. It is integrated into Innovus, resulting in an increased fixing rate. This is timing and DRC aware, resulting in fast closure. DFM PM process hotspot check is mandatory and integrated into Innovus.

IR Drop

The digital full flow is IR-aware throughout the flow, leaving just a few outliers to the end of the design cycle. This is in contrast with the traditional method of ignoring IR drop until the end and then attempting to fix everything at once.

Results

Insertion of triple voting flops had a negligible impact on design characteristics.

DFM hotspots eliminated.

No IR issues. Maximum drop 66.5mV versus a 129mV criterion.

Summary

Reference flow for delivering automotive safety, quality, and reliability using Samsung Foundry 14LPU and Cadence Implementation and Signoff
Demonstrated on Tensilica ConnX B10 DSP IP—meaningful for automotive radar, lidar, and V2X communications products
Minor impact to PPA from safety mechanisms
Integrated flow critical to prevent PPA impact from quality and reliability

Learn More

See the Tensilica ConnX product page ConnX DSPs for Radar, Lidar, and Communications.

See the digital full flow product page Digital Design and Signoff.

See the Cadence Automotive Solutions page.

See the Samsung SAFE EDA Reference Flow page.

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