TSMC: N7, N6, N5

TSMC has such a large market-share of the foundry business that their roadmap is the de facto roadmap for many of the largest fabless semiconductor companies. In a normal year, I look forward to the TSMC Technology Symposium in April. It is the main place during the year that TSMC reveals details of their processes. They typically discuss not just process details, but when IP and flows will be certified and available, when fabs will ramp. On an even longer timeframe, what new fabs are planned or under construction. As I said, this is the main event during the year when the process roadmap for the fabless industry is laid out in some detail.

The Tech Symposium this year has been postponed. However, some of the press releases that would have gone out that week are crossing the wire anyway, since they would be out of date by late summer.

In my blog post from OIP about process status (see above) I said:

At TSMC OIP today, Cadence announced the certification of the Cadence EDA tool portfolio on TSMCs N6 and N5P processes. We also announced that we are working on customers on N6 design starts for both production designs and test chips, and have an active N5P customer engagement underway. This certification covers both the Cadence digital and signoff tools, as well as the custom/analog tools. I'm not going to list them all here. There is more detail in the press release. Note that Cadence previously announced the certification of digital and analog tool flows for N5 (at last year's OIP). The one-sentence summary is that all Cadence tools are supported on all available TSMC processes.

Note that N5P is going away as a process with its own name. It is being folded into N5 with the V1.1 PDK.

Cadence and TSMC are working closely with customers on production designs on TSMC’s advanced processes including N7, N6, and N5, and have enabled tape-outs across the world on these leading-edge processes. PDKs for all these processes are available for download.

TSMC Announcement: 5nm Fab in Arizona

At the end of last week, on 15th May, TSMC put out a press release, the meat of which is:

TSMC today announced its intention to build and operate an advanced semiconductor fab in the United States with the mutual understanding and commitment to support from the U.S. federal government and the State of Arizona. This facility, which will be built in Arizona, will utilize TSMC’s 5-nanometer technology for semiconductor wafer fabrication, have a 20,000 semiconductor wafer per month capacity, create over 1,600 high-tech professional jobs directly, and thousands of indirect jobs in the semiconductor ecosystem. Construction is planned to start in 2021 with production targeted to begin in 2024. TSMC’s total spending on this project, including capital expenditure, will be approximately US$12 billion from 2021 to 2029. This U.S. facility not only enables us to better support our customers and partners, it also gives us more opportunities to attract global talents. This project is of critical, strategic importance to a vibrant and competitive U.S. semiconductor ecosystem that enables leading U.S. companies to fabricate their cutting-edge semiconductor products within the United States and benefit from the proximity of a world-class semiconductor foundry and ecosystem.

Substitute Tech Symposium

Since the Tech Symposium is months away, here is my substitute report, based on what TSMC presented at last year's OIP (September 2019) and at IEDM (December 2019).

TSMC OIP: 6nm and 5nm

This post includes what I call the secret decoder ring to TSMC process names (5-7nm version):

• N7 is the 7nm process in full volume production without EUV
• N7+ is the second-generation 7nm process using some EUV layers, also in full volume production
• N6 is a shrink of N7+ giving more performance and an 18% logic density gain
• N5 is the 5nm process, in risk production during OIP last year, now in full volume production

This post also contains a lot of links to earlier posts about TSMC processes, if you want to go further back than OIP 2019 and IEDM 2019.

TSMC OIP: Process Status

There is a huge amount of detail in this post, not just on the advanced nodes (N5, N6, N7) but also specialty processes for low power and RF. Plus, not really a process, but increasingly important in building large systems, advanced packaging. There is too much to summarize here, but the final bullets presented were:

• N5 is ready, risk production started in March 2019, they are receiving customer product tapeouts [this is now in production]
• TSMC is continuing to advance new technology with N7 going to N6, N16 going to N12, N28 going to N22
• TSMC has a comprehensive RF platform
• Comprehensive 3D-IC design ecosystem to enable product innovation

Details of TSMC's IEDM Presentation on N5

This was a presentation at last year's International Electronic Devices Meeting (IEDM) held in San Francisco last December. TSMC gave limited device-level details of their 5nm process. This was not entirely new information since TSMC have given some details on N5 at both the Tech Symposium and OIP last year (see above for links to my posts about them).

Here's my summary paragraph:

Bottom line: TSMC has developed a 5nm process that will be in high-volume manufacturing very soon (first half of 2020) with a planned "fastest ramp ever". The previous fastest ramp was roughly going from a standing start to 50,000 wafers-per-month over three months. Given TSMC's market share of the foundry business, this is presumably the most significant process for the next couple of years. If you buy a new phone late this year, it will almost certainly contain some chips built in it. Next...3nm. 

Of course, that 5nm process is now in HVM.

IEDM: TSMC on 3nm Device Options

This was also a presentation from IEDM, part of the logic (as opposed to memory) short course that takes place on the Sunday before the conference itself opens. As such, it is more of a tutorial on 3nm and not a roadmap presentation. For example, it covers the pros and cons of nanosheets, but TSMC has already said that 3nm will be FinFET. Here is his summary slide:

At TSMC’s 1Q20 earnings last month, TSMC said that its 3nm process will offer another full-node stride with 70% logic density gain, 10-15% speed gain, 25-30% power improvement compared to it N5.

EUV

The biggest story in lithography over the last decade has been the development of EUV. I won't recap the entire story. But as it happened, ASML's CEO gave one of the plenary keynotes at IEDM. ASML, based in the Netherlands, is the only company that makes EUV steppers. I wrote up his keynote, which is a recent overview of where EUV is and where it will go in my post IEDM 2019: An Overview...Plus the Future of EUV. There is an even more complete history in my post IEDM: EUV, the Road to HVM and Beyond which is a 2019 post based on IEDM in December 2018.

But here is a one-paragraph summary. Until EUV, we have had to use lithography based on 193nm lasers. With optical proximity correction, the industry could print features with a pitch of 80nm with single patterning. That got us to 20nm. From then on, lithography on the tightest layers needed to be double patterned (also called LELE for litho-etch-litho-etch). As we continued to lower nodes, we required triple (LE3) and quadruple patterning (LE4), self-aligned double patterning (SADP), and generally the cost of doing anything went up due to the extra masks and all the extra process steps required. EUV has a light source of 13.5nm and so could do all these multi-patterned layers with single patterning. All semiconductor manufacturers, including TSMC, wanted to introduce EUV several process generations earlier than they did. But EUV had some major challenges, which you can read about in more detail in the posts I already linked to above.

I have confessed before that I was an EUV skeptic that these problems would not be solved in a way that would make EUV manufacturing economic. I was half-right, in the sense that EUV was so late that it never became economic until second-generation 7nm, when it was getting close to being too late to avoid the need to use double patterning even for EUV. Plus, on the economic aspect, EUV steppers are insanely expensive, with prices rumored to be around $150M per stepper.

For a look at the future of EUV, see Greg Yeric's presentation from Arm TechCon 2019 where he predicts the $1B stepper in 2030. I reported on his talk in my post Arm TechCon: A Look at 2020 and 2030. The graph above is not Moore's Law, it is how the cost of a stepper has increased over time. And yes, it's a logarithmic scale, so it is actually exponential.

TSMC EUV Introduction

TSMC took a cautious approach to introducing EUV, designing their initial 7nm process, N7, to use multiple-patterning and 193nm light. When EUV was working, they could switch out multiple-patterning for fewer masks and processing steps without needing to change the designs. But once that was working, they could go further and take advantage of tightening design rules to reduce area, and get an increase in performance. This process is called N7+. They could then shrink that further to N6 (with the same design rules other than the shrink). At the next generation, 5nm, EUV was taken as given, resulting in N5. Of course, all subsequent processes will assume EUV for the lower layers.

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