Update: Pointwise, PCIe, RISC-V

19 Apr 2021

Update: Pointwise, PCIe, RISC-V

This is another of my occasional update posts, covering changes to recent posts that are not big enough to justify an entire post on their own. Today, Pointwise and PCIe. You will almost certainly have to read further to discover who Pointwise is. You almost certainly already know what PCIe and RISC-V are.

Pointwise

Cadence has continued to expand its multiphysics portfolio with the acquisition last week of Pointwise. Pointwise addresses computational fluid dynamics (CFD) meshing for aerospace. So it is a complement to our recent acquisition of NUMECA, which you can read about in my previous posts:

When the dust settles, I will interview some people at Pointwise and get a bit more color. In fact, I can't wait. As it says on their website:

Since 1984, mesh generation software from Pointwise and its co-founders has been used for CFD preprocessing on applications as diverse as aerodynamic performance of the F-35 Lightning II and reducing fish mortality rates in a hydroelectric project.

It is not just the F-35 Lightning II.

Pointwise's meshing software has been applied to virtually every major military aircraft and spacecraft in the last 30 years including the F-16, F-15, F-18, F-22, F-35, F-117, B-2, E-2C, P-3C, Space Shuttle, Space Station, and more.

But don't you really want to find out about the fish?

PCIe 5.0

I always find it hard not to say "PCIe Express" when I am talking. But, of course, the "e" already stands for express. I used to work for a company called "VaST Systems Technology" where the "ST" in "VaST" already stood for "Systems Technology" so I guess I got trained to be redundant.

I recently wrote a history of PCIe in my post The History of PCIe: Getting to Version 6. I also wrote about the previous version (gen 4) in my posts:

Recently, Cadence has published a video showing some of the operation of its PCIe 5.0 interface. You can watch the video below or at Cadence sub-system for PCIe 5.0 – Silicon Demo. Approximately 5 minutes.

Learn more on the Discover PCIe5 page.

RISC-V (and Tensilica)

RISC-V is sometimes dismissed as being "academic". It is true that, in the last decade, it has taken over in academia, since it is pretty much the only instruction set that is simple enough for teaching, and also doesn't come with lawyers like x86 and Arm. In industry, the most well-known usage is in the control processor inside NVIDIA's GPUs, and in Western Digital (fka SanDisk) flash and SSD controllers.

My most recent RISC-V posts were:

Last week, SiFive, the company that is at the spearhead of commercializing the ISA (including the team that originally designed the ISA) announced that they taped out 5nm silicon of a RISC-V processor using HBM 3 memory in an advanced package. I think more details will be discussed at this week's Linley Processor Conference. Cadence's Tensilica team is presenting there, too: Vision and AI DSPs for Ultra-High-End and Always-On Applications. I will have a Breakfast Bytes post on the presentation, so look for that later in the week.

For now, on the SiFive 5nm tapeout, you'll have to make do with this paragraph from the press release:

The SoC features an OpenFive High Bandwidth Memory (HBM3) IP subsystem and D2D I/Os, as well as a SiFive E76 32-bit CPU core. The HBM3 interface supports 7.2Gbps speeds allowing high throughput memories to feed domain-specific accelerators in compute-intensive applications including HPC, AI, Networking, and Storage. OpenFive’s low-power, low-latency, and highly scalable D2D interface technology allows for expanding compute performance by connecting multiple dice together using an organic substrate or a silicon interposer in a 2.5D package.

This is a test chip for the IP blocks, and is not expected to be used for real without further customization.

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