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Featured

Virtuoso Studio IC25.1 ISR3 Now Available

Virtuoso Studio IC25.1 ISR3 production release is now available for download.

KomalJohar
• 4 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Announcement blog

Virtuoso Studio IC25.1 ISR2 Now Available

Virtuoso Studio IC25.1 ISR2 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Spectre 25.1 Release Now Available

The SPECTRE 25.1 release is now available for download at Cadence Downloads. For…

SpectreReleaseTeam
• 1 min read
featured , Spectre FMC Analysis , Spectre RF , Spectre Photonics , Spectre AMS Designer
Analog/Custom Design
Latest blogs

SKILL for the Skilled: Part 4, Many Ways to Sum a List

In the previous posts SKILL for the Skilled: Many Ways to Sum a List (Parts 1, 2…

• 5 min read
Team SKILL , Virtuoso IC6.1.5 , Jim Newton , sum a list , SKILL for the Skilled , recursion , Virtuoso , Lisp , SKILL++

ARM-Based Microcontrollers using Cadence’s Mixed-Signal Solution

I recently came across a Wall Street Journal article, "ARM Chases Bigger Slice of…

• 2 min read
DAC , microcontrollers , Demo , Cortex-M , MCUs , Virtuoso , Cortex-M0 , incyte , fuel injection system , System Design Kit , micro-controllers , ARM , Balasubramanian

SKILL for the Skilled: Part 3, Many Ways to Sum a List

In Part 1 and Part 2 of this series of posts, I showed a couple of ways to sum up…

• 4 min read
recursive functions , Team SKILL , Jim Newton , sum a list , SKILL for the Skilled , recursion , Virtuoso , Lisp , Custom IC Design , SKILL++

SKILL for the Skilled: Part 2, Many Ways to Sum a List

In the previous posting, SKILL for the Skilled: Many Ways to Sum a List (Part 1 …

• 4 min read
Team SKILL , Jim Newton , sum a list , summing , Virtuoso , software development , SKILL++ , SKILL

Things You Didn't Know About Virtuoso: The (Setup) State of Things

Apologies for the long delay between articles (best intentions and all that). I last…

• 3 min read
Variability Aware Design , Analog Design Environment , Virtuoso IC6.1.5 , setup states , IC615 , analog , IC 6.1.5 , ADE , Virtuoso Analog Design Environment , Virtuoso , ADE-GXL , Analog Design Environment , ADE-XL , Custom IC Design

SKILL for the Skilled: Part 1, Many Ways to Sum a List

A while back I presented a one day SKILL++ seminar to a group of beginner and advanced…

• 3 min read
Jim Newton , sum a list , summing , Virtuoso , apply , software development , SKILL++ , sumlist , SKILL

Mixed Signal Design IP Embraces Metric-Driven Verification Using RNM

Even though it's been over 2 months since this year's Design Automation Conference…

• 3 min read
real number modeling , DAC , uvm , IP , A/MS , Verilog-AMS , analog , co-simulation , Mixed-Signal , analog behavioral models , analog/mixed-signal , model validation , RNM , metric-driven verification , VHDL-AMS , assertions , mixed signal , mixed-signal design , wreal , real number models , Design Automation Conference , SPICE , mixed-signal verification , verification , stmicroelectronics , real number

Mixed-Signal Gets Clear Message in China

While most of my colleagues in the US were taking a nice break during the July 4…

• 3 min read
mixed-signal seminars , Beijing , AMS , China , mixed signal design , Technology on tour , mixed-signal ToT , mixed-signal methodology , mixed signal methodology , tech on tour , mixed signal solution , analog , Mixed-Signal , Shenzhen , mixed signal methodology guide , mixed signal , ARM , tech-on-tour , Shanghai , AMS Verification , mixed-signal verification

Tech-On-Tour: Bringing Advanced Mixed-Signal Design Methodology from Concepts to…

About a year ago, Cadence offered a worldwide Tech-On-Tour (ToT) series for mixed…

• 1 min read
DAC , Technology on tour , mixed-signal methodology , tech on tour , CPF , Mixed-Signal , encounter , Virtuoso , Cortex-M0 , incyte , mixed signal , Mixed-Signal Methodology Book , tech-on-tour , OpenAccess

What’s Hot for Mixed-Signal At DAC?

Analog/mixed-signal design is a hot topic at the Design Automation Conference! At…

• 2 min read
DAC , AMS , mixed signal design , mixed-signal methodology , mixed signal methodology , mixed signal solution , 28nm , 20nm , Advanced Node , Mixed-Signal , mixed signal physical implementation open access , mixed-signal book , mixed signal methodology guide , low-power design , mixed signal , cortex M , mixed-signal design , power , Design Automation Conference , mixed signal implementation , digitally assisted analog , mixed-signal verification

Cadence To Release the Industry's First Mixed-Signal Methodology Book

The new era of “Internet Everywhere” creates a whole new spectrum of applications…

• 1 min read
AMS , mixed signal design , mixed-signal methodology , mixed signal methodology , mixed signal solution , analog , Mixed-Signal , mixed-signal book , dac2012 , mixed signal methodology guide , Mixed signal physical implementation , DAC 2012 , mixed-signal design , mixed signal implementation , mixed-signal verification

Managing Inherited Connections with CPF in Virtuoso

Let's assume you are managing a schematic-driven top level design in Virtuoso and…

• 4 min read
inherited connections , EDI , Low Power , mixed signal solution , CPF , analog , Mixed-Signal , encounter , Verilog , mixed signal physical implementation open access , Virtuoso , oa , Mixed signal physical implementation , mixed signal , OA: OpenAccess , mixed-signal design , Virtuoso environment , mixed signal implementation , design implementation , Common Power Format

Things You Didn't Know About Virtuoso: Rapid Adoption Kits

This post isn't directly about tips and tricks for getting the most out of Virtuoso…

• 1 min read
Virtuoso IC6.1.5 , Rapid Adoption Kit , workshop , analog , Constraint-driven , Virtuoso , ViVA , Connectivity-driven , Custom IC Design , RAKs , Virtuoso Layout Suite XL

A Quick Tutorial on Managing ECOs Using Pcells in Mixed Signal Designs

The purpose for creating a Pcell is to automate the creation of data. Pcells should…

• 3 min read
ECO , Static timing analysis , EDI , mixed signal design , parasitic , IC 6.1 , mixed signal solution , Open Access , STA , timing model , ECOs , mixed-signal ECOs , Mixed-Signal , encounter , Virtuoso , oa , EDIS , ECOs and PCells , Mixed signal physical implementation , mixed signal , signoff , OpenAccess , Virtuoso environment , mixed signal implementation

What is Digitally Assisted Analog Design?

Mixed-signal applications are among the fastest growing segments in the electronics…

• 2 min read
daa , AMS , Low Power , mixed signal design , mixed signal solution , Mixed-Signal , dac2012 , Mixed signal physical implementation , mixed signal , cortex M , DAC 2012 , ARM , boris murmann , digitally assisted analog , mixed-signal verification

CDNLive! -- Real Number Model Development and Application in Mixed-Signal SoC Ve…

With the escalating complexity of analog mixed-signal (AMS) chips, increasing digital…

• 3 min read
real number modeling , CDN Live , CDNLive SV 2012 , CDNLive , AMS Designer , LSI , RNM , behavioral models , CDNLive! , wreal , Luo , Virtuoso environment , AMS Verification , mixed-signal verification , verification

Things You Didn't Know About Virtuoso: Change is Here to Stay

Speaking of variation -- and isn't everyone these days -- something strikes me in…

• 4 min read
Variability Aware Design , Analog Design Environment , Virtuoso IC6.1.5 , custom/analog , IC 6.1 , Analog Simulation , IC615 , analog , IC 6.1.5 , ADE , Virtuoso Analog Design Environment , variability , Virtuoso , ADE-GXL , Analog Design Environment , ADE-XL , Variation , IC 6.1.4 , Custom IC Design , change

DVCon 2012: Bringing Continuous Domain into SystemVerilog Covergroups

On the last day of February 2012, I presented a proposal at the DVCon 2012 Conference…

• 2 min read
SystemVerilog , coverage , covergroups , Functional Verification , analog , Mixed-Signal , DVcon , real number types , functional coverage , mixed signal , floating point , mixed-signal verification , verification , real number

Learn How to Do Mixed-Signal Design at CDNLive! Silicon Valley

With the theme of Connect, Share and Inspire, this year's CDNLive! Silicon Valley…

• 2 min read
real number modeling , APS , Low Power , mixed signal design , CDNLive SV 2012 , parasitic , IC 6.1 , AMS Designer , CPF , analog , Mixed-Signal , analog behavoral , Virtuoso , RNM , CDNLive! , mixed signal , simulation , verification

Virtuoso AMS Designer Wins the China ACE Best EDA Product Award

The China Annual Creativity in Electronics (ACE) Awards was established to recognize…

• less than a min read
AMS , Virtuoso-AMS , China , mixed signal design , ACE award , AMS-Designer , AMS Designer , Mixed-Signal , wreal

SKILL for the Skilled: Introduction to Classes -- Part 5

In the previous SKILL for the Skilled postings, we looked at a pretty good algorithm…

• 4 min read
Team SKILL , programming , Sudoku , object orientation , Virtuoso , Lisp , Custom IC Design , SKILL++ , SKILL

Things You Didn't Know About Virtuoso: Measurements Across Corners

In Virtuoso IC 6.1.5 ISR6, we released a new feature in ADE XL, which had been requested…

• 1 min read
Corners , Virtuoso IC6.1.5 , custom/analog , IC 6.1 , Corners analysis , IC615 , IC 6.1.5 , Virtuoso Analog Design Environment , Virtuoso , Analog Design Environment , ADE-XL , Custom IC Design

Things You Didn't Know About Virtuoso: We've Got You Cornered

One of the big buzzwords around the EDA world these days is "variation." Don't you…

• 3 min read
Corners , Analog Design Environment , Virtuoso IC6.1.5 , custom/analog , IC615 , analog , IC 6.1.5 , ADE , Virtuoso Analog Design Environment , Virtuoso , Analog Design Environment , ADE-XL , Custom IC Design , corner analysis

Improved IDF Tool Automatically Fixes Design Rule Violations in Virtuoso

Although many automatic layout generation tools are available to automate design…

• 6 min read
design rule violations , IC615 , analog , IC layout , IC 6.1.5 , Virtuoso , error correction , IDF , Custom IC Design , layout optimization , layout correction , interactive design fixing

Behavioral Model Validation with amsDmv

a msDmv (Analog Mixed Signal Design and Model Validation) is an application integrated…

• 4 min read
AMS , Mixed-Signal , analog behavoral , model validation , Virtuoso , behavioral models , mixed signal , amsDMV

Cadence is the OpenText Connectivity Partner of the Year

Cadence is pleased to be honored by the OpenText Global Partners Program as their…

• less than a min read
ExceedOn Demand , OpenText , Exceed on Demand , remote access , analog , connectivity partner , Open Text , Virtuoso , Custom IC Design

SKILL for the Skilled: Introduction to Classes -- Part 4

In several previous postings we introduced the problem of solving the sudoku puzzle…

• 6 min read
Team SKILL , programming , Sudoku , object orientation , Virtuoso , Lisp , Custom IC Design , SKILL++ , SKILL

Fred Discovers 1000x-10000x Speedup Using wreal Models

This is the second installment in an ongoing series of blog posts that includes an…

• 1 min read
real value , Verilog-AMS , analog , Mixed-Signal , analog behavoral , Verilog , Virtuoso , Fred , mixed signal , wreal , SPICE
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