Virtuosity: Custom IC Design Flow/Methodology - Circuit Physical Verification & Parasitic Extraction

The current challenge in custom/mixed-signal design is to have a fast and silicon-accurate methodology. In this blog series, we are exploring the Custom IC Design Flow and Methodology stages. This methodology directly addresses the primary challenge of predictability in creating these IC designs, by maximizing speed and silicon accuracy throughout the design process. The methodology also covers the key design domains of analog, custom digital, and RF, and supports their integration with digital standard cell blocks. 

Design Flow Stages

The figure below illustrates the five key design stages in Custom IC design methodology and the various Cadence tools one can use in each stage. In this blog, which is the fourth one in the Custom IC design Flow/Methodology series, we will be covering the Circuit Physical Verification and Parasitic Extraction design stage, which is performed after the layout is created. We will also talk about a related Rapid Adoption Kit that is available on Cadence Learning and Support portal for you to download for free and use as a test set up to try out the various design stages in the flow. 

Physical Verification

After creating the layout, our focus shifts to Physical Verification. Physical Verification is the process of checking if the IC layout can work as intended, ensuring adherence to the acceptable performance and efficiency levels. The checks that are run at this stage in the flow focus on design rule checking (DRC) and layout-versus-schematic (LVS) checking.

Design Rule Check (DRC)

Design rule checking (DRC) determines if a layout design satisfies the rules defined by the foundry. What this typically implies is that a DRC run examines the shape of each layer in the layout against the DRC rules, and flags any violations of rules such as minimum spacing, minimum width, minimum overlap, and so on.

Each semiconductor manufacturing process has its own set of rules and ensures sufficient margins such that normal variability in the manufacturing process does not result in chip failure.

DRC violation: Metal2 wire is placed too close to another Metal2 wire

Layout versus Schematic (LVS)

Layout vs. Schematic (LVS) check provides device and connectivity comparisons between the circuit layout (physical representation) and the schematic (logical representation). The schematic is considered as Golden. Owing to the errors that may have been introduced during layout creation, the two circuit representations may not be identical. But for the physical circuit to behave as intended, the two design representations must be identical.

LVS uses Virtuoso StreamOut and CDLout utilities to convert DFII layout and DFII schematic into GDSII and CDL, respectively. Then LVS extracts the devices and connectivity information from GDSII layout using the extract rules deck and creates a SPICE netlist of the layout. This is followed by the comparison between the layout netlist and the schematic netlist. If differences are found (device mismatch, parameter mismatch, connectivity mismatch, shorts, opens, and so on), a mismatch report is created. You can see and debug the mismatches using LVS Debug Environment.

LVS violation: M2_M1c via is missing, creates an “open”

Parasitic Extraction

Finally, when a layout design is verified as being robust and in compliance with the source schematic and the design rules, we're ready to call in Quantus Extraction Solution to help with parasitic extraction. During parasitic extraction, Quantus Extraction Solution extracts the parasitic resistance and capacitance from the metal interconnects and saves them in a format that can be easily analyzed during netlisting and simulations. The parasitic netlist is further used in the post-layout simulation to investigate the effects of these parasitic resistors and capacitors on the circuit. The netlist is also used for IR drop and electromigration (EM) analysis.

Parasitics visible in the extracted view

To try out the Custom IC Design flow, you can download a series of RAKs from the Cadence Learning and Support website. In this RAK series, each stage in the Custom IC Design Flow and Methodology is explained in detail, supported by a downloadable test database to help you try out the steps. The RAK series begins at the introduction of the design flow, followed by the schematic and layout design of the Sample and Hold ADC block, which is then followed by a pre-layout simulation setup and run. Then the RAK covers extraction of the individual blocks inside the top-level Flash ADC design, followed by a final post-layout simulation analysis to ensure the pre- and post-layout results are consistent and the specifications are met. The GDSII (Graphic Database System II) file is created as a final step, which can then be sent to the foundry for fabrication. You can run each stage in the RAK independently, or work your way through the entire flow.

To read more about the next design stage — Post-Layout Circuit Simulation — in the Custom IC Design flow, stay tuned for our next blog in the series.

For more information on Cadence Custom IC circuit design products and services, visit www.cadence.com.

Related Resources

Rapid Adoption Kits	Custom IC Design Flow/Methodology  Custom IC Design Flow/Methodology: Schematic Capture & Circuit Simulation Custom IC Design Flow/Methodology: Circuit Layout Custom IC Design Flow/Methodology: Circuit Physical Verification and Parasitic Extraction
User Guides​	Virtuoso Schematic Editor User Guide Virtuoso Layout Suite XL User Guide Cadence Physical Verification User Guide Quantus Extraction Users Manual Virtuoso Glossary
Blogs	Virtuosity: Custom IC Design Flow/Methodology – Introduction Virtuosity: Custom IC Design Flow/Methodology – Schematic Capture and Circuit Simulation Virtuosity: Custom IC Design Flow/Methodology – Circuit Layout

Contact Us

For any questions or general feedback, please write to custom_ic_blogs@cadence.com.

Happy reading, and stay safe!

Harinarayan Yadav, Ashish Patni

About Virtuosity

Virtuosity has been our most viewed and admired blog series for a long time. The series has brought to the fore some less well-known yet very useful software and documentation improvements and has also shed light on some exciting new offerings in Virtuoso. This series broadcasts the voices of different bloggers and experts, who continue to preserve the legacy of Virtuosity and try to give new dimensions to it by covering topics across the length and breadth of the Virtuoso environment, and a lot more. Subscribe to receive email notifications about our latest Custom IC Design blog posts.