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Hi readers! Welcome to Veri-Fire, a blog series that helps you deep dive into Virtuoso® ADE Verifier and learn about its various whys and hows. In this series, Walter Hartong, a Product Engineering Architect at Cadence, will be answering some frequently asked questions on Virtuoso ADE Verifier. Stay tuned for some interesting explanations and solutions! And if you have any specific questions in mind, feel free to send those to veri-fire@cadence.com.  
You can find most of the questions that come across to Walter on the Virtuoso ADE Verifier FAQ page, and the list might grow, depending on your questions ! 

In the past few weeks, you must have explored episode 1, episode 2, and episode 3 of our Veri-Fire series. In this episode of Veri-Fire, we are back with a few more interesting questions and answers for you. 

Domenico: What is a 'mapping' in Virtuoso ADE Verifier, and why do we need it? How do we do it?

Walter: Interesting question! And here's the answer in this video:

Nikita: My digital verification team uses vManager. Can Virtuoso ADE Verifier provide them the data? 

Walter: Yes, it can! Virtuoso ADE Verifier has a really good connection to vManager. In fact, the early ideas of the tool were based on reusing vManager. We soon figured out that a standalone implementation inside the Virtuoso platform is more appropriate, but still the structure and a lot of the ideas are based on vManager.

I would recommend you to take a look at the Verifier-vManager video which will give you a great introduction of the flow. Also, there is a Virtuoso ADE Verifier RAK ready for you to download and try out.

Doug: For what group size do you think is Virtuoso ADE Verifier useful?

Walter: The larger the group, the higher is the need for structure and formal communication. This means a higher value-add is possible when using Virtuoso ADE Verifier. Having said that, the tool can be useful even for individual designers.

If you were working with ten Virtuoso ADE Assembler cellviews for a project, Virtuoso ADE Verifier can give you a detailed verification status of all the ten cellviews (or a subset) by letting you add them in. I am sure you will agree that can be quite beneficial.

Now, if you were working with 3-5 folks in a team, I see that the detailed verification status can be of significant value. If you are a team of more than 10, it is probably time to look into a hierarchical setup of Virtuoso ADE Verifier. The following video also discusses this topic.

Ian: Can I do “What If” analysis in Virtuoso ADE Verifier without impacting the data of all the designers?  

Walter: Before I say 'Yes', let me say that the initial idea of Virtuoso ADE Verifier is to "not touch" the Virtuoso ADE Assembler or the design setup. There are very few features that can change the setup of Virtuoso ADE Assembler. In most cases, we assume that the Virtuoso ADE Assembler setup is exactly the way it should be and that Virtuoso ADE Verifier does not update it.

But yes, Virtuoso ADE Verifier can update the Virtuoso ADE Assembler setup too, if you want it to. Before you do that, be sure that you are ready with your design cycle and all the verification is done. 

Let us know if you found this episode of Veri-Fire helpful, or if you have a question!  
Also, do check out the Related Resources section for more details. 

Related Resources

For more information on Cadence circuit design products and services, visit www.cadence.com.

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Happy reading, and stay safe!

Team ADE Verifier