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Featured

Virtuoso Studio IC25.1 ISR2 Now Available

Virtuoso Studio IC25.1 ISR2 production release is now available for download.

Virtuoso Release Team
Virtuoso Release Team 23 Oct 2025 • 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Spectre 25.1 Release Now Available

The SPECTRE 25.1 release is now available for download at Cadence Downloads. For…

SpectreReleaseTeam
SpectreReleaseTeam 5 Aug 2025 • 1 min read
featured , Spectre FMC Analysis , Spectre RF , Spectre Photonics , Spectre AMS Designer

Accelerating RFIC EM Analysis with EMX Planar 3D Solver in Virtuoso HI Platform

In modern IC design, especially with the rise of heterogeneous integration, electromagnetic…

Pratul Nijhawan
Pratul Nijhawan 3 Jun 2025 • 6 min read
blended , blended training , featured , Virtuoso Studio , Virtuoso System Design Environment
Analog/Custom Design

Latest blogs

Things You Didn't Know About Virtuoso: Rapid Adoption Kits

This post isn't directly about tips and tricks for getting the most out of Virtuoso…

stacyw 22 May 2012 • 1 min read
Virtuoso IC6.1.5 , Rapid Adoption Kit , workshop , analog , Constraint-driven , Virtuoso , ViVA , Connectivity-driven , Custom IC Design , RAKs , Virtuoso Layout Suite XL

A Quick Tutorial on Managing ECOs Using Pcells in Mixed Signal Designs

The purpose for creating a Pcell is to automate the creation of data. Pcells should…

paragb 16 May 2012 • 3 min read
ECO , Static timing analysis , EDI , mixed signal design , parasitic , IC 6.1 , mixed signal solution , Open Access , STA , timing model , ECOs , mixed-signal ECOs , Mixed-Signal , encounter , Virtuoso , oa , EDIS , ECOs and PCells , Mixed signal physical implementation , mixed signal , signoff , OpenAccess , Virtuoso environment , mixed signal implementation

What is Digitally Assisted Analog Design?

Mixed-signal applications are among the fastest growing segments in the electronics…

QiWang 30 Apr 2012 • 2 min read
daa , AMS , Low Power , mixed signal design , mixed signal solution , Mixed-Signal , dac2012 , Mixed signal physical implementation , mixed signal , cortex M , DAC 2012 , ARM , boris murmann , digitally assisted analog , mixed-signal verification

CDNLive! -- Real Number Model Development and Application in Mixed-Signal SoC Ve…

With the escalating complexity of analog mixed-signal (AMS) chips, increasing digital…

AElzeftawi 9 Apr 2012 • 3 min read
real number modeling , CDN Live , CDNLive SV 2012 , CDNLive , AMS Designer , LSI , RNM , behavioral models , CDNLive! , wreal , Luo , Virtuoso environment , AMS Verification , mixed-signal verification , verification

Things You Didn't Know About Virtuoso: Change is Here to Stay

Speaking of variation -- and isn't everyone these days -- something strikes me in…

stacyw 5 Apr 2012 • 4 min read
Variability Aware Design , Analog Design Environment , Virtuoso IC6.1.5 , custom/analog , IC 6.1 , Analog Simulation , IC615 , analog , IC 6.1.5 , ADE , Virtuoso Analog Design Environment , variability , Virtuoso , ADE-GXL , Analog Design Environment , ADE-XL , Variation , IC 6.1.4 , Custom IC Design , change

DVCon 2012: Bringing Continuous Domain into SystemVerilog Covergroups

On the last day of February 2012, I presented a proposal at the DVCon 2012 Conference…

PrabalB 30 Mar 2012 • 2 min read
SystemVerilog , coverage , covergroups , Functional Verification , analog , Mixed-Signal , DVcon , real number types , functional coverage , mixed signal , floating point , mixed-signal verification , verification , real number

Learn How to Do Mixed-Signal Design at CDNLive! Silicon Valley

With the theme of Connect, Share and Inspire, this year's CDNLive! Silicon Valley…

QiWang 7 Mar 2012 • 2 min read
real number modeling , APS , Low Power , mixed signal design , CDNLive SV 2012 , parasitic , IC 6.1 , AMS Designer , CPF , analog , Mixed-Signal , analog behavoral , Virtuoso , RNM , CDNLive! , mixed signal , simulation , verification

Virtuoso AMS Designer Wins the China ACE Best EDA Product Award

The China Annual Creativity in Electronics (ACE) Awards was established to recognize…

QiWang 28 Feb 2012 • less than a min read
AMS , Virtuoso-AMS , China , mixed signal design , ACE award , AMS-Designer , AMS Designer , Mixed-Signal , wreal

SKILL for the Skilled: Introduction to Classes -- Part 5

In the previous SKILL for the Skilled postings, we looked at a pretty good algorithm…

Team SKILL 10 Feb 2012 • 4 min read
Team SKILL , programming , Sudoku , object orientation , Virtuoso , Lisp , Custom IC Design , SKILL++ , SKILL

Things You Didn't Know About Virtuoso: Measurements Across Corners

In Virtuoso IC 6.1.5 ISR6, we released a new feature in ADE XL, which had been requested…

stacyw 9 Feb 2012 • 1 min read
Corners , Virtuoso IC6.1.5 , custom/analog , IC 6.1 , Corners analysis , IC615 , IC 6.1.5 , Virtuoso Analog Design Environment , Virtuoso , Analog Design Environment , ADE-XL , Custom IC Design

Things You Didn't Know About Virtuoso: We've Got You Cornered

One of the big buzzwords around the EDA world these days is "variation." Don't you…

stacyw 26 Jan 2012 • 3 min read
Corners , Analog Design Environment , Virtuoso IC6.1.5 , custom/analog , IC615 , analog , IC 6.1.5 , ADE , Virtuoso Analog Design Environment , Virtuoso , Analog Design Environment , ADE-XL , Custom IC Design , corner analysis

Improved IDF Tool Automatically Fixes Design Rule Violations in Virtuoso

Although many automatic layout generation tools are available to automate design…

Hiro Ishikawa 13 Dec 2011 • 6 min read
design rule violations , IC615 , analog , IC layout , IC 6.1.5 , Virtuoso , error correction , IDF , Custom IC Design , layout optimization , layout correction , interactive design fixing

Behavioral Model Validation with amsDmv

a msDmv (Analog Mixed Signal Design and Model Validation) is an application integrated…

xiuya 30 Nov 2011 • 4 min read
AMS , Mixed-Signal , analog behavoral , model validation , Virtuoso , behavioral models , mixed signal , amsDMV

Cadence is the OpenText Connectivity Partner of the Year

Cadence is pleased to be honored by the OpenText Global Partners Program as their…

NewYorkSteve 28 Nov 2011 • less than a min read
ExceedOn Demand , OpenText , Exceed on Demand , remote access , analog , connectivity partner , Open Text , Virtuoso , Custom IC Design

SKILL for the Skilled: Introduction to Classes -- Part 4

In several previous postings we introduced the problem of solving the sudoku puzzle…

Team SKILL 14 Nov 2011 • 6 min read
Team SKILL , programming , Sudoku , object orientation , Virtuoso , Lisp , Custom IC Design , SKILL++ , SKILL

Fred Discovers 1000x-10000x Speedup Using wreal Models

This is the second installment in an ongoing series of blog posts that includes an…

Paul Foster 1 Nov 2011 • 1 min read
real value , Verilog-AMS , analog , Mixed-Signal , analog behavoral , Verilog , Virtuoso , Fred , mixed signal , wreal , SPICE

How Fred Discovered Mixed-Signal Behavioral Modeling

Introduction This is the first of a series of blogs where we will add pieces to the…

Paul Foster 31 Oct 2011 • 3 min read
AMS , mixed signal design , AMS-Designer , Verilog-AMS , analog , Mixed-Signal , Virtuoso , Fred , assertions , mixed signal , wreal

A Moment to Mourn -- John McCarthy, Father of Lisp

Here lies a Lisper Uninterned from this mortal package Yet not gc'd While we…

Team SKILL 31 Oct 2011 • 1 min read
John McCarthy , McCarthy , software development , Lisp , Custom IC Design , SKILL

SKILL for the Skilled: Introduction to Classes -- Part 3

In the previous posting Introduction to Classes -- Part 2 we saw the high level…

Team SKILL 17 Oct 2011 • 8 min read
Team SKILL , programming , Sudoku , classes , IC 6.1.5 , object orientation , Virtuoso , Lisp , Custom IC Design , SKILL++ , SKILL

Managing ECOs in Mixed Signal Designs

Imagine you are days away from completing the implementation of a fairly complex…

Benatcdn 29 Sep 2011 • 3 min read
ECO , Farhat , mixed signal design , CPF , Open Access , Floorplanning , ECOs , mixed-signal ECOs , Mixed-Signal , encounter , Virtuoso , oa , Mixed signal physical implementation

SKILL for the Skilled: Introduction to Classes -- Part 2

In the previous posting Introduction to Classes -- Part 1 we introduced the problem…

Team SKILL 5 Sep 2011 • 3 min read
Team SKILL , programming , object orientation , Virtuoso , Lisp , SKILL++ , SKILL

Bringing Static Analysis Methods to Mixed Signal Designs

Accurate static analysis and complete coverage of the functional space remain very…

archive 26 Aug 2011 • 2 min read
Static timing analysis , static analysis , mixed signal design , full timing model , STA , timing model , analog , FTM , Mixed-Signal , Signal Integrity , OpenAccess , SPICE , liberty model , .lib

SKILL for the Skilled: Introduction to Classes -- Part 1

In the previous couple of SKILL for the Skilled postings, we looked at some of the…

Team SKILL 15 Aug 2011 • 3 min read
Sodoku , Team SKILL , programming , classes , object orientation , Virtuoso , object system , Lisp , Custom IC Design , SKILL++ , SKILL , Allegro

Virtuoso Analog Design Environment XL – Data Everywhere, But You Have a Review in…

In my previous blogs , I talked about productivity enhancing features of Virtuoso…

archive 29 Jul 2011 • 2 min read
analog , ADE , Virtuoso , Analog Design Environment , Virtuoso datasheets , Schematic Editor , Custom IC Design , datasheets

Things You Didn't Know About Virtuoso: Viva ViVA!

I realize that I have been quite remiss in that I have not yet blogged about the…

stacyw 8 Jul 2011 • 1 min read
Analog Design Environment , ViVa-XL , Virtuoso IC6.1.5 , Analog Simulation , IC 6.1.5 , Virtuoso Analog Design Environment , Virtuoso , ViVA , ADE-XL , Custom IC Design

Synchronizing Designs and Behavioral Models in Mixed-Signal Flows

The creation of behavioral models is only one part of the process of using those…

Paul Foster 6 Jul 2011 • 3 min read
AMS , Virtuoso-AMS , mixed signal design , AMS-Designer , amsDMVAMS-Designer , Verilog-AMS , analog , Mixed-Signal , model validation , mixed signal , wreal

M/S Technology on Tour Blog – Model Validation and Assertion Based Verification

In February 2011, I had the opportunity to meet a group of analog and mixed-signal…

PrabalB 28 Jun 2011 • 5 min read
Virtuoso-AMS , mixed-signal ToT , amsDMVAMS-Designer , Mixed-Signal , SVA , model validation , Virtuoso , PSL , assertions , mixed signal

How to Design Analog/Mixed Signal (AMS) at 28nm

Wireless, networking, storage, computing and FPGA applications have been moving…

nizic 21 Jun 2011 • 3 min read
AMS , AMS v2.0 , APS , Virtuoso-AMS , IP , AMS-Designer , reference flow , 28nm , TSMC , analog , Mixed-Signal , LDE , Virtuoso , Spectre , mixed signal
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