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Featured

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera 31 Jul 2025 • 2 min read

Transforming Chip Design with Cadence Cerebrus AI Studio

Cadence is transforming chip design with the launch of Cadence Cerebrus ® AI Studio…

Sean Kobayashi 11 Jun 2025 • 1 min read

digital design , featured , agentic ai , designed with cadence , Cadence Cerebrus

Conformal AI Studio: Accelerated LEC/ECO/LP with AI/ML-Driven Enhancements

If you're a chip designer or verification engineer, you have likely spent countless…

David Stratman 13 Mar 2025 • 5 min read

conformal , featured , Digital Implementation , Conformal AI Studio , AI/ML

Digital Design

Latest blogs

Encounter Puzzler: Where Did My Fences Go?

A while back I visited a customer I see on a fairly regular basis. As soon as I entered…

BobD 8 Sep 2010 • 1 min read

fences , Floorplanning , encounter , Digital Implementation , puzzler

CDNLive! Silicon Valley Abstract Deadline Extended 1 Week

The deadline for submitting abstracts to CDNLive! Silicion Valley 2010 has been extended…

BobD 25 Aug 2010 • less than a min read

CDNLive!

Webinar: SOI Gives More Performance Per Watt, And There's An Easy Path

If you've seen any of the recent buzz lately around Silicon-On-Insulator (SOI),…

archive 20 Aug 2010 • less than a min read

Low Power , webinars , Low-Power , Power-Efficient Design , Digital Implementation , Silicon on Insulator , Power Analysis , mixed signal , SOI , power

Abstracts For CDNLive! Silicon Valley 2010 Due August 22

Don't let the name CDNLive! confuse you. It's the Cadence user's group conference…

BobD 9 Aug 2010 • 2 min read

Floorplanning , hierarchical design , Digital Implementation , CDNLive! , tcl

EDA Follow-The-Leader ... Signoff In The Design Flow

As a member of the EDA community, I find it interesting and somewhat frustrating…

PeteMc 9 Aug 2010 • 1 min read

Programmatically Capturing Cell Delay In The Encounter Digital Implementation Sy…

A while back we were talking about how to programatically troubleshoot timing violations…

BobD 23 Jul 2010 • 5 min read

Static timing analysis , CTE-TCL , Digital Implementation , scripting , tcl

DAC 2010 – A “Coming Out” Party For 3D-IC Design

Overall, the 2010 Anaheim DAC was livelier than the years before. Customer and vendor…

RahulD 28 Jun 2010 • 2 min read

DATE , CSV , 3DIC , TSV , Wirebond , Digital Implementation , 3D , stacked die , flip chip , PoP

Mixed Signal: Why The Sudden Attention?

With DAC 2010 rapidly approaching, we can again expect that lots of EDA and IP vendors…

PeteMc 24 May 2010 • 2 min read

DAC , SoC , Mixed-Signal , Digital Implementation , mixed signal

What you didn’t know about DFM for advanced node designs: “In-route” is insuffic…

Recently, there has been a lot of buzz about addressing DFM issues during routing…

Manoj Chacko 14 May 2010 • 3 min read

Digital Implementation forums , DRC , design rules , EDA , Encounter Digital Implementation System 9.1 , Manufacturability sign-off , Digital Implementation , Encounter Digital Implementation , EDI system Encounter Digital Implementation System , DFM

Hands Up, Anyone Believe That Toyota's Problems Are All Physical?

In the past number of weeks/months we have all seen how Toyota has struggled to manage…

PeteMc 26 Apr 2010 • 2 min read

toyota , Digital Implementation , BMW , microprocessor , verification

EDP Symposium Uncovers an Inconvenient Truth with a Shot of 3D

Every April the leading edge of the leading edge of semiconductor industry meet…

RahulD 16 Apr 2010 • 3 min read

DATE , CSV , 3DIC , TSV , Wirebond , Digital Implementation , stacked die , flip chip , PoP

IR Drop Analysis: It's Not Really Necessary, Is It?

I was recently asked by an engineering manager if running IR drop analysis was really…

PeteMc 5 Apr 2010 • 2 min read

VDD , VDD I/O , Digital Implementation , IR drop , EM Failures

My DATE With 3DIC Technology

This year DATE (Design, Automation and Test in Europe) was in snowy cold Dresden…

archive 29 Mar 2010 • 3 min read

DATE , CSV , 3DIC , TSV , Wirebond , Digital Implementation , stacked die , flip chip , PoP

Signoff-Driven Implementation = Consistent and Convergent = Predictable and Effi…

Digital designs are reaching 10's of millions of instances, which makes efficiency…

archive 10 Mar 2010 • 2 min read

timing system , dynamic rail analysis , Static timing analysis , Early Rail Analysis , Multi-Core and Parallel rocessing , Statistical , Extraction , Signoff Analysis , timing constraints , SI analysis , noise analysis , OCV , Signal Integrity , Digital Implementation , Timing analysis , Power Analysis , signoff , timing convergence

Encounter How To: Writing To/Reading From a File With TCL

A couple weeks ago, there was a good thread in the Digital Implementation Forums…

BobD 24 Feb 2010 • 2 min read

EDI system , encounter digital implementation system , Digital Implementation , Closure , Foundation Flow Design , scripting , tcl

User Review of The Encounter Foundation Flow

This is a guest post from John McGehee. John is an independent consultant in Silicon…

BobD 22 Feb 2010 • 4 min read

Foundation Flow , Encounter Digital Implementation System 9.1 , scripting , Encounter Digital Implementation System 8.1

Three Reasons to Move to EDI System 9.1

We recently announced the 9.1 version of the Encounter Digital Implementation System…

BobD 1 Feb 2010 • 1 min read

Foundation Flow Design Closure , Encounter Digital Implementation System 9.1 , Digital Implementation , EDI system Encounter Digital Implementation System

Encounter Screencast: Editing Wires More Quickly With Bindkeys

The Encounter Digital Implementation System offers interactive wire editing capabilities…

BobD 21 Jan 2010 • 1 min read

Wire Editor , encounter digital implementation system , Digital Implementation , bindkeys

Sometimes It's The Little Things: Working With Square Brackets in Encounter

Good news! A long-standing source of irritation for Encounter users has been addressed…

BobD 15 Jan 2010 • 1 min read

Ease of Use , Encounter Digital Implementation System 8.1

Design Signoff Begins In Implementation

As an ex-design engineer now working in EDA, I am often privileged to see advanced…

PeteMc 6 Jan 2010 • 1 min read

dynamic rail analysis , Static timing analysis , SI , Early Rail Analysis , ets , cadence , EDI system , Signoff Analysis , encounter digital implementation system , EPS , Signal Integrity , Cadence Encounter Power System , Digital Implementation , crosstalk , CeltIC , tapeout , design closure , encounter power system , Encounter Timing System , timing convergence , "SoC-Encounter" , blog