Featured

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML

Transforming Chip Design with Cadence Cerebrus AI Studio

Cadence is transforming chip design with the launch of Cadence Cerebrus ® AI Studio…

Sean Kobayashi
• 1 min read
digital design , featured , agentic ai , designed with cadence , Cadence Cerebrus

Conformal AI Studio: Accelerated LEC/ECO/LP with AI/ML-Driven Enhancements

If you're a chip designer or verification engineer, you have likely spent countless…

David Stratman
• 5 min read
conformal , featured , Digital Implementation , Conformal AI Studio , AI/ML
Digital Design

Latest blogs

Lost and Found: Missing Filler Cells, Power Vias, and Highlighted Objects

Have you ever gotten to signoff DRC and found that there was a small area where a…

• 2 min read
power vias , filler cells , highlighted objects , checkFiller , 8.1 , Digital Implementation , verifyPowerVia , "SoC-Encounter" , F9

Co-Design - Its Not Just an Exercise in Excel Any More - Learn Why at the Aug. 26…

Co-Design … some are trying to do it with spreadsheets … everyone is talking about…

• 1 min read
SoC-Encounter , Cadence SiP , Co-Design , Digital Implementation , FlipChip

Useful dbGet One-Liners

We've gotten some good feedback about posts in this forum relating to dbGet and dbSet…

• 2 min read
dbGet , dbSet , Digital Implementation

5 Fascinating People I Met at the 2009 Design Automation Conference

As much as the Design Automation Conference (DAC) is about demonstrating solution…

• 5 min read
DAC , Digital Implementation

Reducing Risk and Improving Productivity with the Cadence InCyte Chip Estimator and…

I'm looking forward to heading out to San Francisco next week for the 46th Design…

• 1 min read
DAC , Digital Implementation , Cadence InCyte Chip Estimator , Encounter Digital Implementation System 8.1

How To: Create a Self-Contained Testcase in Encounter

In the course of performing design work in Encounter, it frequently becomes desireable…

• 2 min read
Digital Implementation forums , How To , testcase , Encounter Digital Implementation System 8.1

Using A Dual Flop Methodology for Dynamic Power Savings

Imagine this scenario: Your chip is a low power design. You’ve used everything in…

• 1 min read
Low Power , dual flop , Digital Implementation

Flow? What Flow?

For EDA software, it seems that it takes just as much effort to develop a methodology…

• 1 min read
Foundation Flow , EDI system , encounter digital implementation system , Digital Implementation , design closure

Cadence: Committed to DFM

On June 10, Cadence issued a press release that mentioned “…decreasing the level…

• 1 min read
Advanced Node , Mixed-Signal , encounter , Virtuoso , Manufacturability sign-off , Digital Implementation , DFM

Technical Webinars Hosted by the Experts - Don't Miss Them!

Starting June 23, 2009, Cadence technical experts will host a series of technical…

• 1 min read
Low Power , webinars , advanced design , design planning , Digital Implementation , physical implementation , timing convergence

MarCom 2009 - New, Exciting, Educational

As a Marketing Communications professional, I am always looking for creative ways…

• 2 min read
EDI , EDI system , encounter digital implementation system , Digital Implementation

Getting Started with dbSet

A while back, I posted a blog called Getting Started with dbGet . It was a brief…

• 2 min read
dbGet , dbSet , encounter , Digital Implementation

EDA Industry Stays Ahead of Technology Curve

The EDA Industry is the unsung hero behind for modern era electronic revolution since…

• 2 min read
DAC , EDI , Multi-Core , Virtuoso , Parallel rocessing , Digital Implementation , DFM

Interview with SiRF's Nigel Foley on Low-Power Design

Over the last three years, customers have been able to leverage the Cadence Low-Power…

• 4 min read
digital Implementationg , Low Power , encounter 8.1 , Low-Power , encounter , Logic Design , Digital Implementation , Encounter Digital Implementation , Encounter Digital Implementation System 8.1

VoltageStorm Is Alive and Kicking!

If your only news source were some of the common EDA pundits, you would likely believe…

• 2 min read
timing system , ets , voltagestorm , EPS , Digital Implementation , encounter power system

WiMAX and the Road to Complete Independence From Network Cables: Sequans Communication…

Step into any Starbucks hotspot or Wi-Fi cafe, and you'll see something that was…

• 3 min read
Low Power , encounter 8.1 , Power-Efficient Design , SoC-Encounter" , Cadence Encounter Power System , Digital Implementation , The Power Forward Initiative , Encounter Digital Implementation , Encounter Digital Implementation System 8.1

Noise Induced Double Clocking Explained

In my previous blog on noise analysis accuracy , I mentioned something called “double…

• 1 min read
CadMOS , encounter , Digital Implementation , double clocking , Enouter Timing System , CeltIC

Constraint Construction: What's Its Function? Part 4 of 4

This is the last in the series of Constraint Construction blogs ! Today we're going…

• 2 min read
design rules , encounter , rtl compiler , Digital Implementation , modes of operation

Encounter Digital Implementation System 8.1 San Jose Live Blog

I'll be live blogging from the Cadence Campus in San Jose today. We're doing a seminar…

• less than a min read
Low Power , encounter , Digital Implementation , mixed signal , design closure , Encounter Digital Implementation System 8.1

Great Article by Freescale: Timing Convergence Accross the Flow is "Very Important…

Having consistency and correlation in timing analysis across the design flow is …

• less than a min read
EDN , encounter , Digital Implementation , Encounter Timing System

Get on Board With Bus Guides

One of the coolest new things in Encounter 8.1 is Bus Guides. I know many of you…

• 2 min read
Bus Guides , encounter , 8.1 , Digital Implementation

'Back to School' in April? Are you Kidding?

No, I am not kidding. in fact, we have planned several 'back to school' seminars…

• 1 min read
digital Implementationg , Low Power , encounter 8.1 , Low-Power , encounter , Manufacturability sign-off , 8.1 , Digital Implementation , "SoC-Encounter" , Encounter Digital Implementation System 8.1

Does Noise Analysis Accuracy Really Matter?

There have been a lot of new faces springing up in the signoff analysis market over…

• 2 min read
Static timing analysis , Signoff Analysis , STA , Advanced Node , Mixed-Signal , 8.1 , Encounter Digital Implementation , CeltIC NDC , Global Timing Debug , SSTA , "SoC-Encounter"

How To Use I/O Rows - It's a Snap!

Have you ever tried manually moving IO cells in your design and thought: "This would…

• 1 min read
encounter 8.1 , Floorplanning , Digital Implementation , i/o rows

Talk "Low Power" With The Experts

I am very excited about an event that Cadence low-power R&D and technical experts…

• less than a min read
Low Power , Digital Implementation forums , Low-Power , Power-Efficient Design , encounter , Logic Design , 8.1 , Digital Implementation , Encounter Digital Implementation , Encounter Digital Implementation System 8.1 , verification

Constraint Construction: What's Its Function? Part 3 of 4

Part 3. EXCEPTION PATHS: For Every Rule, There Is An Exception More often than not…

• 2 min read
Constraint Design , STA , Encounter Digital Implementation , Encounter Timing System

Demo: Automatic Floorplan Synthesis in Encounter

As an Applications Engineer, the first demonstrations you deliver of a new technology…

• 1 min read
MasterPlan , Floorplanning , Digital Implementation , Encounter Digital Implementation System 8.1

Turning the Downturn Upside Down

Many bemoan the gloom and doom of the present economic situation, and it is true…

• 1 min read
Low Power , OVM , MIPI , encounter , Virtuoso , Spectre , Digital Implementation , Chi-Ping
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