Voltus^TM IC Power Integrity Solution is a power integrity and analysis signoff solution that is integrated with the full suite of design implementation and signoff tools of Cadence to deliver the industry’s fastest design closure flow.

The aim of this blog series is to broadcast the voices of different experts on how design engineers can effectively use the diverse Voltus technologies to achieve high-performance, accuracy, and capacity for next-gen chip designs.

While helping my nephew reach a critical level in his combat and colony-builder video game, we discovered a useful hack to limit aggressive enemies to specific sectors. This enabled us to deal with different fighting monsters or fire-breathing dragons at our pace and advance by eliminating each group separately without using all our weapons simultaneously. This valuable hack inspired me to think of the different strategies our IC engineers need to develop in order to deal with the complex design constraints that need to be tamed before a powerful yet efficient solution can emerge. Wouldn’t it be useful to know the exact power target that a region or circuit block can endure with the intent of creating a low-power design? This brings us to our new vectorless methodology, “Target Power Analysis,” for managing power consumption.

Why Vectorless Dynamic IR Drop Analysis

With shrinking design cycles and advanced node power challenges, designing an “Optimal Power Grid” that is robust across multiple operating scenarios is extremely crucial for SoC design. Large SoCs require several simulation/switching activity patterns to cover all the use case scenarios. Generating these patterns and validating power grid robustness for each of these is not feasible. Furthermore, accurate patterns are not available until the end of the design cycle, leaving very little time for the ECO cycles. Issues such as the enormous size of advanced node designs, long simulation runtime, and availability of vectors late in the game, make vectorless power analysis the best option for designers looking to improve their productivity. Vectorless power analysis enables designers to perform different scenario-based dynamic-voltage-drop (DVD) analyses and achieve better results.

Target Power Vectorless Methodology for Designer-Centric Power Analysis

Voltus Target Power analysis utilizes the user-defined power targets for full-chip power analysis. The flow enables designers to specify the power targets for full-chip, physical block, logical block, and power/ground net. When these targets are specified, Voltus will automatically scale the toggle rates of the clock gate ratio, input, macro, and sequential activities to meet the designer-specified power targets. The flow provides an option to adjust activity for the user-defined power such that the average static power in DVD should be within user define limit (5%). The vectorless flow enables 100% instance toggle coverage, thus catching the worst drop instances. The average current of dynamic IR drop analysis is like the average power in the target power vectorless analysis. Designers can add power constraints for a region to check specific block and region dynamic IR drop weaknesses.

What Does Target-Power Vectorless Methodology Mean for Me?

In the Target Power flow, designers can constrain the design by providing power targets that guide the tool to exercise paths (event-propagation based method that simulates the realistic scenario) to complete the IR drop analysis. This methodology helps to model local power/local peak current demand accurately in the absence of a vector, leading to faster and optimal toggle coverage, balanced power, and user-defined power-oriented Dynamic Voltage Drop.

Some of the key benefits of this flow are:

• Provides a linear prediction technique to adjust the activity parameters
• Achieves end activities within user-defined power target (user configurable) with marginal runtime increase
• Supports options to fix/adjust clock gate ratio, input, and macro activities
• Supports power specification based on physical/logical hierarchy and PG nets
• Allows to specify multiple power targets on the same design (Total, hierarchy, and PG net-based target)
• Supports cycle-by-cycle user-defined switching scenario

How Does Target Power Vectorless Power Analysis Work?

The following diagram shows the target power flow:

The flow uses varying activity numbers for sequential, input, macro, and clock gate activities. The iterations stop when the achieved power is within the tolerance limit. The activities from the final iteration are used to simulate current construction. Target Power allows you to specify different power optimization constraints by determining the portions of the design with varying power needs, as shown below:

These power optimization techniques make it easy to check the region or block’s DVD weakness for a given power value. The following diagram illustrates the DVD hotspot correlation between power-guided region-based dynamic vectorless run and VCD-based dynamic run:

Here,

• Hotspot areas are clearly identified for power-guided region-based dynamic vectorless run.
• Hotspot and non-hotspot areas were well correlated with the VCD run.

Summary

The power target methodology with user-defined power comprehensively supports early identification of grid weaknesses from the region or block-based peak power demands without using vectors. The new power solution can be leveraged to meet the design challenges in terms of scalability, design coverage, and runtime, thus stepping up the power signoff game from the traditional approach to a game changer.

Related Resources

For more information on Cadence digital design and signoff products and services, visit www.cadence.com/go/voltushs.

About Voltus Voice

“Voltus Voice” showcases our product capabilities and features, and how they empower engineers to meet time-to-market goals for the complex, advanced-node SoCs that are designed for next-gen smart devices. In this monthly blog series, we also share important news, developments, and updates from the Voltus space.

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