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Cadence Welcomes VLAB Works

Cadence welcomes VLAB Works, a division of Australian Semiconductor Technology Corporation…

Corporate
• less than a min read
Automotive , featured , Virtual Development Environment , vlab , Protium

Time on Your Side: Launching PSS Perspec Composer

We all agree that time is precious. As PSS ( Portable Stimuli Standard ) models get…

OK202502201742
• 3 min read
featured , Perspec , pss , portable stimulus

Cadence Announces Industry's First Verification IP for Embedded USB2v2 (eUSB2v2)

USB Promoter Group has released the eUSB2® Version 2.0 specification (eUSB2v2) in…

Sanjeet Kumar
• less than a min read
Verification IP , eUSB2v2 , featured , Functional Verification , USB
Verification

Latest blogs

Flash Memory Demystified: Nor Flash Vs. Nand Flash

In the world of flash memory, two primary types dominate the market: NOR flash and…

• 4 min read

Navigating the Complexity of Address Translation Verification in PCI Express 6.0

The Address Translation Service (ATS) is a crucial process in the Peripheral Component…

• 5 min read
Verification IP , Functional Verification , VIP , PCIe

Beyond Gigabit: Navigating the Terrain of 1600G Ethernet Networks

In the ever-evolving landscape of networking technologies, the arrival of 1600G Ethernet…

• 2 min read
Verification IP , Ethernet VIP , Functional Verification , VIP , Ethernet standards , Ethernet , Ethernet PHYs , ethernet 1600G

Verisium SimAI: Machine Learning for Efficient Design Verification

Are you tired of spending hours on tedious tasks like debugging and coverage closure…

• less than a min read
ml , coverage , Functional Verification , bugs , verisium , DV , machine learning , SimAI , xcelium , AI

Pre-Silicon Software Execution and Performance Validation – A Case Study

In a persistent trend, shrinking IC geometries and higher levels of integration are…

• 12 min read
prototyping , Protium , Emulation , FPGA

Lightmatter Matters - Photonics-Based Verification with Xcelium Mixed-Signal App

Traditionally, analog mixed signal (AMS) verification works by utilizing a connection…

• 3 min read
lightmatter , mixed signal , xcelium , bind-to-spice

Training Insights: Reaching Your Verification Closure Using Verisium Manager

For a while now, Cadence has led the Verification Planning and Management (VPM) domain…

• 2 min read
Functional Verification , System Design and Verification , verisium , Verisium Manager , vManager , verification

Verifying SoC BootROM Using Standard Verification Techniques

BootROM is still found in system-on-chip (SoC) designs, especially where security…

• 4 min read
ROM , coverage , BootROM , verification

Training Insights – A Brand New Free Online Course on UCIe VIP Introduction

The Cadence VIP portfolio is used to provide various standard protocol VIPs for testing…

• 3 min read
digital badge , live training , blended training , ucie , online_training , Verification IP , VIP , Training Insights

Weak Verification Plans Lead to Project Disarray - How to Fix That

The purpose of the verification plan, or vplan as we call it, is to capture all the…

• 2 min read
coverage , quality , debug , vPlan , Verisium Debug , vManager

The Year That Was: Training Insights Training Bytes Blog and Video Highlights from…

As we welcome 2024 now we will not miss to look back at our most-viewed blogs of…

• 2 min read
digital badge , online_training , System Design and Verification , Protium , blended_training , training , webinar , training bytes , Verisium Debug

What Is Viral in CXL 3.0?

Introduction to CXL 3.0 CXL 3.0 is an open-standard interconnect technology that…

• 3 min read
CXL , Verification IP , viral , Functional Verification

Understanding Embedded USB2 (eUSB2) and its usage

The need for higher processing power and lower power consumption are driving processors…

• 2 min read
VIP , USB , eUSB2

Unraveling PCIe 6.0 Loopback and Digital Near-End Loopback Feature

PCIe spec has given a specific LTSSM state named Loopback , which is intended for…

• 2 min read
PHY , NELB , Loopback , Gen6 , PCIe 6.0

DisplayPort 2.1 vs DisplayPort 1.4: A Detailed Comparison of Key Features

DisplayPort is a digital display interface developed by the Video Electronics Standards…

• 2 min read
Verification IP , Functional Verification , DisplayPort

Building Verification Infrastructure for Complex PCIe Verification

Introduction PCIe (Peripheral Component Interconnect Express) is a high-speed serial…

• 4 min read
Verification IP , Functional Verification , PCIe , pcie gen6

Navigating Cache Coherence: The Back-Invalidate Feature in CXL 3.0

In the rapidly evolving landscape of data centers, ensuring cache coherence in multi…

• 2 min read
CXL , performance , Verification IP , Functional Verification , coherent , HIgh Speed Interconnect

Automate Regression Failure Triage with the Cadence Verisium

Have you ever experienced the frustration of fixing a bug during the design stage…

• 3 min read
Versium , Auto Triage , Regression

Revolutionize System Verification Flow with a Holistic Approach

The increasing functionality of designs is leading to a noticeable rise in the complexity…

• 3 min read
wholistic approach , system level , System Level Design Verification , verification

Ethernet Encryption: Harnessing the Power of IPSec Shields

In the ever-expanding domain of interconnected devices and digital communication…

• 2 min read

Leveraging AI to Optimize the Debug Productivity and Verification Throughput

The impact of semiconductors on various sectors cannot be overstated. Semiconductors…

• 5 min read

Insights Into the Evolutions and Optimizations of PCIe 6.0

The PCIe prot ocol (Peripheral Component Interconnect Express) had its first generation…

• 4 min read
Verification IP , VIP , PCIe , Optimize , pcie gen6 , PCIe 6.0

Maximise Verification Reuse with Cadence Perspec System Verifier

Are You Tired of Countless Hours Manually Creating Complex System-Level Coverage…

• 4 min read
verification reuse , perspec system verifier , Coverage Level Ststem Driven tests , system-level verification , SoC level test suit

USB4 Version 2.0 – Link Configurations

USB4 Version 2.0 specification was released by the USB Promoter Group earlier this…

• 2 min read
USB4 VIP , USB4v2 , usb4 , USB4 Version 2 , usb4 router

Accelerate Your Debug with Verisium - Cadence's Next-Generation Debug Solution

Debugging low-power designs is its own unique challenge in the verification field…

• 3 min read
Low Power , Functional Verification , Verisium Debug , VerisiumDebug

Be Optimistic About Xcelium's New X-Pessimism App!

In simulation, X-Propagation has been used to track how unknown states or signals…

• 2 min read
Functional Verification , x-pessimism , xcelium , simulation

Verifying Compliance During PCIe Re-Timer Testing Poses Challenges

Verifying compliance during PCIe re timer testing poses challenges. Cadence PCIe…

• 4 min read
Re-timer , System Design and Verification , VIP , PCIExpress , compliance , Polling Compliance

USB4 Version 2.0 – Gen4 High-Speed Lane Initialization and Training

USB4 version 2.0 specifications were released by the USB Promoter Group earlier this…

• 3 min read
USB4 VIP , USB4v2 , usb4 , USB4 Version 2 , usb4 router
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