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Cadence Welcomes VLAB Works

Cadence welcomes VLAB Works, a division of Australian Semiconductor Technology Corporation…

Corporate
• less than a min read
Automotive , featured , Virtual Development Environment , vlab , Protium

Time on Your Side: Launching PSS Perspec Composer

We all agree that time is precious. As PSS ( Portable Stimuli Standard ) models get…

OK202502201742
• 3 min read
featured , Perspec , pss , portable stimulus

Cadence Announces Industry's First Verification IP for Embedded USB2v2 (eUSB2v2)

USB Promoter Group has released the eUSB2® Version 2.0 specification (eUSB2v2) in…

Sanjeet Kumar
• less than a min read
Verification IP , eUSB2v2 , featured , Functional Verification , USB
Verification

Latest blogs

More on today's Verification IP portfolio expansion news

Today's announcement on our expanding Verification IP (VIP) portfolio inspired me…

• less than a min read
Functional Verification , Verification IP modeling , multi-language

Getting more value from the OVM using Metric-Driven Verification - Part II

In my last post , I talked about how OVM is a methodology for building automated…

• 1 min read
metric driven verification (MDV) , Functional Verification , OVM , ARM , Incisive Enterprise Simulator (IES)

Early Embedded Systems Conference Coverage

Today, a friend sent me a link to an article on embedded.com that talks about my…

• less than a min read
System Design and Verification , Embedded Systems Boston Conference

Is there a 1 Billion gate chip on your roadmap?

Yes, I'm asking about chips that will have 1 billion -- that's billion with a "B…

• 1 min read
verification strategy , Verification methodology , Functional Verification , System Verification

System-level design and verification - at the center!

This year, Cadence increases its focus on system-level design and verification events…

• 1 min read
Acceleration , System Design and Verification , embedded software , Emulation , ESL handoff , System simulation and analysis , Coverage Driven Verification for Embedded Software , embedded SW engineer , CDNLive! Silicon Valley 2008 , ISX , Hardware/software co-verification , ESL , architect

Power Aware Design Now at System Level

Several years ago, I have purchased a cell phone with a 2 years contract from one…

• 2 min read
Acceleration , System Design and Verification , Low power verification and analysis , system validation/verification engineer , Verification Acceleration , System simulation and analysis , embedded SW engineer , Simulation acceleration , C-to-Silicon Compiler , Hardware/software co-verification , debugging , ESL , architect

An informal introduction

Formal verification can mean different things depending upon who you speak to. If…

• 1 min read
Formal Analysis , Model-checking

Report from last week's "ClubT" events; preview of next week

As promised, here are some photos last week events, with embedded color commentary…

• 1 min read
SystemVerilog , HW/SW , verification strategy , Verification methodology , metric driven verification (MDV) , Functional Verification , Open Verification Methodology , Testbench simulation , OVM , Coverage-Driven Verification , CDV , Multi-domain verification: HW/SW co-verification , ISX (Incisive Software Extensions) , multi-language , coverage driven verification (CDV) , ISX , eRM , System Verification , OVM 2.0 , IES

Users Take Over at CDNLive! 2008

This year I did not attend CDNLive! in San Jose. I wasn't presenting anything and…

• 2 min read
HW/SW , CDNLive San Jose 2008 , Functional Verification' signal integrity , ISX (Incisive Software Extensions)

The cell world

Earlier this Summer, I was lucky enough to attend the CDNLive show in Japan. One…

• 5 min read
IBM , Playstation , Toshiba , cell processor , Sony

In the EU next week for "ClubT" verification events

I'll be in the EU next week supporting "ClubT" events focused on advanced verification…

• 1 min read
SystemVerilog , verification strategy , Verification methodology , metric driven verification (MDV) , Functional Verification , Open Verification Methodology , Testbench simulation , OVM , Coverage-Driven Verification , CDV , Multi-domain verification: HW/SW co-verification , Enterprise Manager , ISX (Incisive Software Extensions) , Plan and metrics management , Verification IP modeling , multi-language , coverage driven verification (CDV) , ISX , eRM , System Verification , OVM 2.0 , IES

Embedded Software Bugging and Debugging

In one of my previous posts I introduced an interesting book titled Dreaming in Code…

• 4 min read
bugging and debugging' , System Design and Verification , embedded software

Getting more value from the OVM using Metric-Driven Verification

With all of the momentum around the OVM these days there has been a lot of good discussion…

• 2 min read
SystemVerilog , Verification methodology , metric driven verification (MDV) , Functional Verification , Open Verification Methodology , Testbench simulation , OVM , Coverage-Driven Verification , CDV , Enterprise Manager , coverage driven verification (CDV) , eRM

Verification community comes together to talk tech

I just finished the week at Cadence's CDNLive User Group in San Jose. Over the past…

• 1 min read
SystemVerilog , Verification methodology , CDNLive , metric driven verification (MDV) , Functional Verification , CDNLive San Jose 2008 , Formal Analysis , Open Verification Methodology , Testbench simulation , OVM , Coverage-Driven Verification , CDV , Enterprise Manager , ISX (Incisive Software Extensions) , Simulation acceleration , coverage driven verification (CDV) , ISX , eRM , System Verification

A few thoughts on CDNLive! and OVM 2.0

My colleague Joe Hupcey has been keeping you informed and entertained with information…

• 1 min read
CDNLive San Jose 2008 , OVM 2.0

OVM 2.0 -- Short Technical Review

By now you may have seen the official announcement of the OVM 2.0 release . So what…

• 3 min read
SystemVerilog , Verification methodology , OVM , CDV , System Verification , OVM 2.0

Day 3 of CDNLive San Jose

Highlights of Day 3: papers all morning, lunch, then closing remarks. Comments on…

• less than a min read
verification strategy , Verification methodology , CDNLive , metric driven verification (MDV) , Functional Verification , CDNLive San Jose 2008 , Multi-domain verification: HW/SW co-verification , Enterprise Manager , ISX (Incisive Software Extensions) , Plan and metrics management , Verification IP modeling , ISX

Day 2 of CDNLive San Jose 2008

Highlights of Day 2: more great papers (with enough customer papers on OVM fill almost…

• less than a min read

Day 1 of CDNLive San Jose 2008

Suffice to say, Day 1 was quite a full day, with the highlight for me being some…

• less than a min read
AMS , CDNLive San Jose 2008 , Multi-domain verification: HW/SW co-verification , multi-language

Enterprise Verification gets a boost (a big one!)

Today we announced important new metric-driven verification capabilities in our enterprise…

• less than a min read
Verification methodology , CDNLive , metric driven verification (MDV) , Functional Verification , Formal Analysis , Coverage-Driven Verification , CDV , Enterprise Manager , Plan and metrics management , coverage driven verification (CDV) , IES

"Day 0" of CDNLive San Jose 2008

Quick report from CDNLive Day 0 (I've labeled it that since this initial day was…

• 1 min read
CDNLive San Jose 2008 , MDV techtorial , System Verification

CDNLive SJ - system design and verification - don't miss it

If you are a system validation/verification engineer, an architect, a power engineer…

• 1 min read
Low Power , power engineer , system validation/verification engineer , embedded SW engineer , architect

See you at CDNLive San Jose next week

FYI, Mike Stellfox and I will be at CDNLive San Jose next week. In addition to reporting…

• less than a min read
Functional Verification , OVM , ISX (Incisive Software Extensions) , IES

Chip Level Verification with Processors

Today, I will discuss some alternatives for chip-level verification with designs…

• 6 min read
verification strategy , Functional Verification , ISX , ARM , FPGA: DMA

The Road to Better Software Verification

It seems the debate over the benefits of better software verification is still alive…

• 5 min read
Intel , Specman , System Design and Verification , Frank Schirrmeister

ESL: The state of the industry and what’s next?

While ESL continues to remain in its infancy, there are signs within the industry…

• less than a min read
System Design and Verification , ASIC/ASSP , advanced process nodes , ESL

Experiences on Marketing a Verification Library

Inspired by JL Gray of the blog "Cool Verification" who stated, in this post: "I…

• 2 min read

Embedded Systems Conference Boston 2008

Friday is that last day to get the Early Bird price for the Embedded Systems Conference…

• 1 min read
System Design and Verification , Coverage Driven Verification for Embedded Software , Embedded Systems Conference 2008 , debugging , Jason Andrews , verification
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