Featured

Cadence Welcomes VLAB Works

Cadence welcomes VLAB Works, a division of Australian Semiconductor Technology Corporation…

Corporate
• less than a min read
Automotive , featured , Virtual Development Environment , vlab , Protium

Time on Your Side: Launching PSS Perspec Composer

We all agree that time is precious. As PSS ( Portable Stimuli Standard ) models get…

OK202502201742
• 3 min read
featured , Perspec , pss , portable stimulus

Cadence Announces Industry's First Verification IP for Embedded USB2v2 (eUSB2v2)

USB Promoter Group has released the eUSB2® Version 2.0 specification (eUSB2v2) in…

Sanjeet Kumar
• less than a min read
Verification IP , eUSB2v2 , featured , Functional Verification , USB
Verification

Latest blogs

iPhone 3G issues - result of HW/SW-co-verification?

In a recent article at cnet, financial analyst said he believes Apple's iPhone 3G…

• 2 min read
Richard Windsor , Infineon 3G chipset , Infineon , System Design and Verification , iPhone 3G , Nomura

ESL gets a new taker

Interesting High-Level Synthesis review by Bryon Moyer at IC Design and Verification…

• less than a min read
High-Level Synthesis , IC Design and Verification , CDNLive! Silicon Valley 2008

Is Concurrent Engineering actually getting worse?

Today I'm taking a few minutes to jot down a few recent observations about the state…

• 3 min read
Concurrent Engineering , System Design and Verification , ISX

OVM - The Methodology for Enabling an Industry-wide VIP Eco-System

As the leader of the Cadence OVM development team, I was reading Richard Goering…

• 3 min read
SystemVerilog , OVM Professionals Network , Verification methodology , Functional Verification , Open Verification Methodology , OVM , Verification IP modeling , eRM , OVMWorld

OVM Leaves the Nest

OK JL , one more marketing post, but this is a good one and even hints at technical…

• less than a min read
Functional Verification , OAG , OVM , OVM Advisory Group , OVMWorld

Putting a face on the OVM

As I recently blogged , there appears to be growing buzz over the Open Verification…

• 1 min read
CDNLive , Open Verification Methodology , OVM

Design space exploration

In his latest blog post Space Exploration ... design is , Grant Martin said that…

• 1 min read
high-level synthesis adoption , System Design and Verification , C-to-Silicon Compiler

Report from the CDV techtorials in SoCal

To follow-up on my previous post on the techtorials, I'm posting some photos from…

• 1 min read
metric driven verification (MDV) , Functional Verification , OVM , coverage driven verification (CDV) , eRM

Flexibility Often Yields Unexpected Results

Often, when engineers set out to build something, the result is different from the…

• 4 min read
Functional Verification , Founders at Work Stories of Startups' Early Days , ISX (Incisive Software Extensions)

OVM is "Open" for Business

Open things are just curiosities until the ecosystem figures out how to turn them…

• 1 min read
SystemVerilog , OVM Professionals Network , Functional Verification , Testbench simulation , OVM , OVMWorld

Transaction-Based Acceleration - Second generation

Transaction-Based Acceleration is becoming more and more important as an extension…

• less than a min read
System Design and Verification

Trip to SoCal "techtorials" on CDV

Just finished packing for a quick trip to Southern California to help kickoff a round…

• 1 min read
Functional Verification , Coverage-Driven Verification , CDV

Is anybody out there a Software Verification Engineer?

In my 2004 book, Co-Verification of Hardware and Software for ARM SoC Design , I…

• 3 min read
co-verification engineer , System Design and Verification , EDA

C-to-Silicon Compiler Launch

On July 14th, Cadence introduced C-to-Silicon Compiler, a next-generation high-level…

• 1 min read
high-level synthesis adoption , C-to-Silicon Compiler

Emulation Drivers - A growing set of selection criteria

Some say that the growth of the emulation market in last few years was driven by…

• 2 min read
Acceleration , System Design and Verification , Emulation , Hardware/software co-verification

The barriers to efficient System Level Design and Verification

The EDA industry been doing system level design and verification for years; we just…

• 1 min read
System Design and Verification

Verification Hierarchy of Needs

Verification consultant Brian Bailey recently started blogging for Chip Design Magazine…

• 2 min read
Verification planning and management , System Design and Verification , Run and Debug

The value of chaos (really!)

Ordinarily chaos is bad thing. Yet like it or not, t he world your SoC lives in is…

• 2 min read
Functional Verification

Why is OVM important for Specman/e customers?

With all of the press and interest from customers adopting it, I am sure most of…

• 2 min read
Verification methodology , Functional Verification , OVM , eRM

Report on the first OVM World Summit at DAC

At the recent Design Automation Conference (DAC) in Anaheim, Calif., Cadence did…

• 1 min read
DAC , Verification methodology , Functional Verification , OVM

'Verification Acceleration' vs. 'Simulation Acceleration'

Simulation acceleration and emulation technology has been commonly used to run faster…

Anonymous • 1 min read
Acceleration , System Design and Verification , Emulation , Verification Acceleration , Simulation acceleration

ESL handoff: closer than you think

Take a look at the article linked below, titled: "ESL handoff: closer than you think…

• less than a min read
System Design and Verification , ESL handoff

Dreaming in Code

One of the best books I read this year is called Dreaming in Code by Scott Rosenberg…

• 2 min read
Dreaming in Code , System Design and Verification , Chandler project

Do you want to buy my chip?

Once upon a time semiconductor companies produced a chip, made a data sheet, showed…

• 1 min read
System Design and Verification , Hardware/software co-verification
Blog - Title