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Cadence Welcomes VLAB Works

Cadence welcomes VLAB Works, a division of Australian Semiconductor Technology Corporation…

Corporate
• less than a min read
Automotive , featured , Virtual Development Environment , vlab , Protium

Time on Your Side: Launching PSS Perspec Composer

We all agree that time is precious. As PSS ( Portable Stimuli Standard ) models get…

OK202502201742
• 3 min read
featured , Perspec , pss , portable stimulus

Cadence Announces Industry's First Verification IP for Embedded USB2v2 (eUSB2v2)

USB Promoter Group has released the eUSB2® Version 2.0 specification (eUSB2v2) in…

Sanjeet Kumar
• less than a min read
Verification IP , eUSB2v2 , featured , Functional Verification , USB
Verification
Latest blogs

Create a Sine Wave Generator Using SystemVerilog

Two capabilities in SystemVerilog allow for the creation of a module that can produce…

• 2 min read
SystemVerilog , AMS , Functional Verification , Incisive , Incisive Enterprise Simulator (IES) , IES , IES-XL

Yikes - Synopsys is Following Me!

No, I'm not being paranoid -- Synopsys, my largest competitor, is literally following…

• 2 min read
Specman , Functional Verification , OVM , OVM e , Coverage-Driven Verification , CDV , e , Twitter , eRM

The Golden Age of Electronics

About a month ago I took my family to The Bakken Museum in Minneapolis, Minnesota…

• 4 min read
System Design and Verification , C-to-Silicon , PCI Express , ESL

Using Constraints to Pass Configuration Options in the Unit Hierarchy (Top-Down approach…

To allow for increased solvability, some constraints that were previously uni-directional…

• 4 min read
IEEE 1647 , IntelliGen , Specman , Functional Verification , e , team specman , Aspect Oriented Programming , Incisive Enterprise Simulator (IES) , AOP , IES-XL

Xilinx SoC FPGAs Ideal Fit For OVM and MDV

Processor-based FPGAs represent 40% of all the design starts today and will rise…

• 1 min read
SystemVerilog , Functional Verification , OVM , Incisive , xilinx , MDV , IES , FPGA

Send Us Suggestions for Updating the e/Specman Quick Reference Card

Team Specman is about to start a project to refresh the e /Specman Quick Reference…

• less than a min read
Specman , Tech Pubs , Functional Verification , e , team specman , Incisive Enterprise Simulator (IES) , IES-XL

Speeding up SystemC compilation with Incisive SystemC

If you’re a C++ and SystemC programmer you know that when you’ve spent all day tracking…

• 6 min read
System Design and Verification , OSCI , embedded software , Incisive , SystemC analysis , George Frazier , System Design & Verification , SystemC , SystemC: OCSI , ESL

VCS Runs OVM -- 2 Years Late, But Welcome None the Less

Something seems to have changed in the Synopsys VCS simulator; the Web2.0 world is…

• 1 min read
SystemVerilog , OVM Professionals Network , Functional Verification , OVM , Incisive , PSL , IES , OVMWorld

New Video on "Metric Driven Verification 101", With Yours Truly Giving the Intro

Recently I had the honor of delivering the introductory section of a detailed demo…

• 1 min read
Verification methodology , metric driven verification (MDV) , Functional Verification , Coverage-Driven Verification , Enterprise Manager

Tip for Linking AMIQ’s DVT to the Specman Docs

Since posting an introductory article and demo on AMIQ’s “DVT” integrated development…

• 2 min read
Specman , Tech Pubs , Functional Verification , tech tips , Incisive , AMIQ , Incisive Enterprise Simulator (IES) , IES-XL

OVM Metric Driven Verification With an FPGA-based Design

During the last 2 years I have enjoyed the opportunity to work with the Incisive…

• 2 min read
System Design and Verification , OVM , Incisive , System simulation and analysis , ISX , Hardware/software co-verification , FPGA

The DWARF Debugging File Format

The Chronicles of Narnia has always been one my favorite series of books. Today,…

• 7 min read
System Design and Verification , DWARF , ARM , ELF , debugging

Enabling OVM Transaction Debug in SimVision Without Code Changes

Are you tired of putting print statements in your code to do debug? Do you work…

• 5 min read
SystemVerilog , debug , Functional Verification , simvision , OVM SV , OVM 2.0 , IES , IES-XL

Tips on Using “vhdlsync” With e+Mixed HDL Simulation

[ Team Specman welcomes Principal Support Application Engineer Avi Farjoun to share…

• 3 min read
AF , Specman , Functional Verification , tech tips , Incisive , e , Verilog , multi-language , Incisive Enterprise Simulator (IES) , VHDL , IES , IES-XL

Team genIES Bloggers Create Simulation Magic

Simulation is a huge topic. Performance, debug, mixed-signal, low-power, assertions…

• 1 min read
Functional Verification , Incisive , OV , IES , IES-XL

Thoughts on the DVClub Talk: "Is it Time to Declare Verification War?"

As noted in a prior post , I had the pleasure of attending a DVClub talk given by…

• 2 min read
verification strategy , metric driven verification (MDV) , Functional Verification , DVClub , MDV

Heads-up: Mixed Signal Verification Webinar (June 10)

For those Specmaniacs using the REAL number data type & ports capabilities in Specman…

• 1 min read
AMS , Specman , verification strategy , Functional Verification , Incisive , e , Incisive Enterprise Simulator (IES) , verification , IES-XL

New IntelliGen Statistics Collection Utilility

As noted in white papers , prior posts , and the Specman documentation, since IntelliGen…

• less than a min read
IEEE 1647 , IntelliGen , Specman , Functional Verification , Incisive , e , team specman , Incisive Enterprise Simulator (IES) , IES , IES-XL

Synthesis Really DOES Need to Change

A great article appeared in Chip Design a few weeks ago written by Tets Maniwa, …

• 2 min read
System Design and Verification , rtl compiler , C-to-Silicon Compiler

Inside Cadence: "Stars & Strikes" charity event

Allow me to make a brief digression from EDA technology blogging to give you all…

• 1 min read
Functional Verification , charity benefit , Stars and Strikes festival

Where's the Bridge to Cross the Great Divide?

At this year's Embedded System Conference in San Jose there was a panel with the…

• 8 min read
windows , dwarfdump , VMware , Embedded Systems Conference 2009 , ISX , Hardware/software co-verification , linux

New "E" text editor and e templates

Imagine Team Specman's surprise when we came across this article on Slashdot about…

• 1 min read
IEEE 1647 , eclipse , Specman , Functional Verification , e , AMIQ , verification , IES-XL

Report from CDNLive! EMEA 2009

CDNLive! in Munich had it all - stimulating customer papers, demonstrations of new…

• 1 min read
ABV , CDNLive , Functional Verification , OVM , VIP , TLA , MDV

Tech Tip: Weighting Generation of "Extreme" Values

[ Team Specman welcomes guest blogger Vitaly Lagoon, an Architect in the Generation…

• 1 min read
IntelliGen , Specman , Verification methodology , Functional Verification , Incisive , e , team specman , Aspect Oriented Programming , Incisive Enterprise Simulator (IES) , IES , AOP , IES-XL

Heads-up: DVClub Boston Coming Up On June 1

Back on March 19 here in Silicon Valley, verification guru Brian Bailey gave a great…

• less than a min read
events , verification strategy , Functional Verification , DVClub

Way Worse Than The Real Thing

This week Cadence and Virtutech announced a collaborative effort to bring together…

• 2 min read
cdnlive! emea 2009 , System Design and Verification , Incisive Enterprise Simulator , embedded software , Incisive , Coverage Driven Verification for Embedded Software , embedded SW engineer , ISX , Hardware/software co-verification , ESL , architect , Virtutech , Coverage Driven Verification

ESL Verification News From CDNLive! EMEA

Hello from CDNLive! EMEA in Munich. Another year has passed, and it’s time…

• less than a min read
System Design and Verification , Incisive Enterprise Simulator , Incisive , SystemC analysis , System simulation and analysis , Coverage Driven Verification for Embedded Software , SystemC , Incisive Software Extensions , Hardware/software co-verification , debugging , ESL , Virtutech , Coverage Driven Verification

System D&V at CDNLive! EMEA

CDNLive! EMEA has started today. I arrived here (Munich Germany) from SFO paying…

• 1 min read
System Design and Verification , Palladium , xtreme , Virtutech
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