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Cadence Welcomes VLAB Works

Cadence welcomes VLAB Works, a division of Australian Semiconductor Technology Corporation…

Corporate
• less than a min read
Automotive , featured , Virtual Development Environment , vlab , Protium

Time on Your Side: Launching PSS Perspec Composer

We all agree that time is precious. As PSS ( Portable Stimuli Standard ) models get…

OK202502201742
• 3 min read
featured , Perspec , pss , portable stimulus

Cadence Announces Industry's First Verification IP for Embedded USB2v2 (eUSB2v2)

USB Promoter Group has released the eUSB2® Version 2.0 specification (eUSB2v2) in…

Sanjeet Kumar
• less than a min read
Verification IP , eUSB2v2 , featured , Functional Verification , USB
Verification
Latest blogs

OVM Is The Safest Bet By 2:1

One of the questions verification engineers will be asking as they head to DVCon…

• 1 min read
SystemVerilog , OVM , VIP , e , DVcon , eRM

The Real Story on HLS With ANSI-C/C++ vs. SystemC

There's a new post worth reading for anyone interested i n the current state of…

• 3 min read

SystemC TLM2 based Virtual Prototype Demo at DVCon

DVCon 2009 promises much news about System level design and verification. With Open…

• less than a min read
co-verification engineer , virtualization , Co-verification link , virtual platform , System Design and Verification , embedded software , Incisive , virual platform , system validation/verification engineer , virtual protoype , System simulation and analysis , Coverage Driven Verification for Embedded Software , embedded SW engineer , Incisive Software Extensions , ISX , Hardware/software co-verification , Jason Andrews , ESL , architect , QEMU

C-to-Silicon Does Not Require a Library Characterization

One of the key strengths of C-to-Silicon Compiler (CtoS) over other ESL Synthesis…

• less than a min read
High-Level Synthesis , high-level synthesis adoption , System Design and Verification , ESC , C-to-Silicon , ESL handoff , C-to-Silicon Compiler , ESL , architect

Blogger of the Quarter Award -- Thanks!!!

Little did I know that when I accepted an innocent looking meeting propsal from my…

• 1 min read
funtional verification , Specman , e

New Blog series- Team ESL

Cadence is well known for its leadership in system verification leveraging its HW…

• 1 min read
High-Level Synthesis , high-level synthesis adoption , System Design and Verification , embedded software , C-to-Silicon , ESL handoff , embedded SW engineer , Incisive Software Extensions , C-to-Silicon Compiler , ISX , Hardware/software co-verification , ESL

Exploring the Virtual Platform Part 4

Welcome to Part 4 of the "Exploring the Virtual Platform" series. For readers just…

• 4 min read
microsoft , System Design and Verification , QEMU virtual platform , vista , ARM , wind river , monta

Road Trip!

As at most companies these days, Cadence is doing what it can to minimize travel…

• 1 min read
Specman , Functional Verification , e , DVcon

Post-Show Thoughts on DesignCon 2009

Joe Hupcey posted some photos from the DesignCon show in Santa Clara last week, and…

• 1 min read
DesignCon , NXP , Functional Verification , coreuse , DVcon

Tech Pubs Tips Series Kickoff: Search for Single Character Words

[Team Specman welcomes the Technical Publications Team to our blog] Effectively documenting…

• 1 min read
Specman , C , e , Enterprise Manager , Incisive Enterprise Simulator (IES) , IES

Tech Tip - Double Wall Clock Performance with One Easy Step

[Please welcome guest blogger Silas McDermott, an Application Engineer in our Field…

• 2 min read
Specman , e , Aspect Oriented Programming , Incisive Enterprise Simulator (IES) , IES , AOP

Scalable OVM Register and Memory Package

Drawing on nearly a decade of experience, Cadence has just posted the first release…

• 2 min read
SystemVerilog , OVM , vr_ad , Register Package , e , eRM

Of EDA Vendors and Conferences

There's an interesting thread on Cool Verification ( http://www.coolverification…

• 1 min read
Functional Verification

Exploring the Virtual Platform Part 3

Welcome to part 3 of the "Exploring the Virtual Platform" series. For readers just…

• 4 min read

Report From DesignCon 2009

This week the " DesignCon " show is in town (<= 10 minutes from the Cadence campus…

• 2 min read
DesignCon , Functional Verification

Good Article Alert: End "EDA Bashing"

Allow me to direct your attention to a most welcome article in EDA DesignLine written…

• less than a min read
Functional Verification , edadesignonline , EDA

Incisive Software Extensions (ISX) vs Co-Verification Link (CVL)

Team Specman has been doing a great job supplying nifty tech tips and other useful…

• 3 min read
CVL , Co-verification link , System Design and Verification , Specmen , Incisive Software Extensions , ISX

Linking C and e: The Co-Verification Link

[Join Team Specman in welcoming guest blogger Jason Andrews. Jason is a recognized…

• 3 min read
Specman , HW/SW , C , e , ISX , Incisive Enterprise Simulator (IES) , Jason Andrews , IES

"...Yes, Virginia there is a Specman"

I usually try to visit many of our customers in Europe (and other parts of the world…

• 3 min read
SystemVerilog , IntelliGen , Specman , metric driven verification (MDV) , Functional Verification , Open Verification Methodology , OVM , Coverage-Driven Verification , e , coverage driven verification (CDV) , Aspect Oriented Programming , eRM , AOP

Interview With Cadence Verification IP Architect Levent Caglar

Even in these challenging economic times, interest in Verification IP ("VIP") has…

• less than a min read
verification strategy , Functional Verification , VIP , Levent Caglar

Tech Tip: Avoiding "Error! Integer Overflow" With Incisive Simulator

While simulating a VHDL design with Incisive Simulator, if an integer overflow is…

• 1 min read
NCVHDL , Functional Verification , Incisive Enterprise Simulator (IES) , IES

"ClubT" Newsletter Issue #3 Just Posted

Specmaniacs and Other Trailblazers, The latest edition of the 'ClubT ' newsletter…

• less than a min read
IEEE 1647 , SystemVerilog , IntelliGen , Low Power , Specman , HW/SW , verification strategy , Verification methodology , metric driven verification (MDV) , Functional Verification , Cadence VIP portfolio , Testbench simulation , OVM , VIP , OVM e , Coverage-Driven Verification , CDV , Multi-domain verification: HW/SW co-verification , e , Enterprise Manager , Enterprise Planner , ISX (Incisive Software Extensions) , Plan and metrics management , coverage driven verification (CDV) , Aspect Oriented Programming , ISX , System Verification , Incisive Enterprise Simulator (IES) , IES , AOP

Functional Verification More Important than Ever in 2009?

Here in Cadence Product Marketing, we're still recovering from our very busy annual…

• 1 min read
metric driven verification (MDV) , Functional Verification , Formal Analysis , Coverage-Driven Verification , coverage driven verification (CDV) , OVM 2.0

Report On The MDV "Deep Dive" Workshops

As heralded in a prior posts, we recently hosted some "alumni" from our recent Techtorials…

• 6 min read
workshops , verification strategy , Verification methodology , metric driven verification (MDV) , Coverage-Driven Verification , Multi-domain verification: HW/SW co-verification , Enterprise Manager , Enterprise Planner , ISX (Incisive Software Extensions) , Plan and metrics management , coverage driven verification (CDV) , ISX , Incisive Enterprise Simulator (IES) , techtorial

Exploring the Virtual Platform Part 2

This week's installment of the "Exploring the Virtual Platform" series focuses on…

• 5 min read
virtual platform , System Design and Verification , ARM , linux , QEMU

Tech Tip: Managing Specman esv File Size

When compiling e files on top of Specman, or when using the save command, Specman…

• less than a min read
Specman , e , Incisive Enterprise Simulator (IES) , IES

Ride The Economy Slow-Down

Last week, at Cadence Sales Kickoff, we have heard fascinating presentations from…

• less than a min read
System Design and Verification , IP re-use , ASIC/ASSP

VIP Following OVM Frees Users to Choose SystemVerilog and e

Back in November Cadence introduced a vastly expanded verification IP portfolio using…

• 1 min read
SystemVerilog , OVM , VIP , e , multi-language , eRM
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