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The Cadence ESL Machine Keeps Building Momentum!

Last week EDN named Palladium DPA a 2009 EDN Innovation Award Winner , and C-to-Silicon…

archive 17 Apr 2009 • 3 min read

System Design and Verification , Palladium , EDN , C-to-Silicon , EDN Innovation award

Performance-Aware e Coding Guidelines – Part 4

Specman 8.2s3 contains a new API to the sequence driver that enables users to improve…

teamspecman 16 Apr 2009 • less than a min read

IEEE 1647 , performance , Specman , Functional Verification , API , tech tips , OVM , OVM e , e , OVM-e , specman elite , sequences , IES , IES-XL

C-to-Silicon Support of Concurrent Processes

Another key differentiator of C-to-Silicon Compiler (CtoS) when compared to C …

TeamESL 15 Apr 2009 • less than a min read

High-Level Synthesis , CTOS , TLM , System Design and Verification , SystemC , ESL

Industry Discussion about High Level Synthesis

Many of you know that Richard Goering has joined Cadence and now writes a blog called…

Steve Brown 14 Apr 2009 • less than a min read

High-Level Synthesis , CTOS , TLM , System Design and Verification , Richard Goering , incisive c-to-silicon

Survey Results For "Booth-Centric" vs. "Paper Centric" Shows

In my last post I shared how my annual tour of the tour of the ESC show floor inspired…

jvh3 14 Apr 2009 • 2 min read

events , DAC , Specman , CDNLive , Functional Verification , CDNLive San Jose 2008 , ESC , DVcon , Xuropa

Performance-Aware e Coding Guidelines – Part 3

The constraint solver is a powerful and fun to use tool. Actually, it is so much…

teamspecman 13 Apr 2009 • 1 min read

performance , Specman , Functional Verification , tech tips , e , specman elite , Incisive Enterprise Simulator (IES) , IES , IES-XL

Homeschoolers Hungry for Technology

Over the weekend I attended the 2009 Minnesota Homeschool Conference in downtown…

jasona 8 Apr 2009 • 4 min read

System Design and Verification , Lego , mindstorms NXT

Tracing TLM 2.0 Activity in an ESL Design – Part 2

In my last post I discussed two ad hoc approaches for tracing TLM 2.0 activity in…

georgef 7 Apr 2009 • 4 min read

System Design and Verification , TLM 2.0 , George Frazier , SystemC , TLM 2.0 Trace

Another New Blog About the e Language

We are compelled to briefly interrupt Efrat's excellent series on Performance-Aware…

teamspecman 7 Apr 2009 • less than a min read

IEEE 1647 , Specman , Functional Verification , e , OVMWorld

Verification of AUTOSAR Software Using a SystemC Virtual Platform

[Please welcome ISX R&D team member Markus Winterholer back to the Team ESL blog…

TeamESL 7 Apr 2009 • 2 min read

AUTOSAR , BSW , System Design and Verification , RTE , SystemC , VFB , ISX

ESC and "Booth-Centric" vs. "Paper Centric" Shows

Last Wednesday I walked the floor of the Embedded Systems Conference (ESC) , with…

jvh3 6 Apr 2009 • 2 min read

events , DAC , CDNLive , Functional Verification , ESC , DVcon

Performance-Aware e Coding Guidelines – Part 2

Building on Part 1 where I talked about the “do’s and don’ts” of List performance…

teamspecman 6 Apr 2009 • 2 min read

performance , IntelliGen , Specman , Functional Verification , tech tips , OVM e , e , OVM-e , specman elite , Incisive Enterprise Simulator (IES) , IES , AOP , IES-XL

Observations From the Embedded Systems Conference

Yes, there was another Embedded Systems Conference this year. Several "multi-year…

Steve Brown 3 Apr 2009 • 2 min read

Embedded Systems Conference , RTL , System Design and Verification , ESL

EDN's 19th Annual Innovation Awards

Two of Cadence system D&V products have been selected as the finalists for the EDN…

Ran Avinun 3 Apr 2009 • 1 min read

System Design and Verification , Palladium , EDN , dpa , C-to-Silicon Compiler

C-to-Silicon Compiler: A High Level and a Low Level Synthesis Tool

Some customers have inquired if C-to-Silicon Compiler (CtoS) is a “Low Level” Synthesis…

TeamESL 3 Apr 2009 • 1 min read

High-Level Synthesis , CTOS , TLM , high-level synthesis adoption , RTL , System Design and Verification , TLM 2.0 , C-to-Silicon , SystemC , C-to-Silicon Compiler , ESL , architect

Is ESL changing EDA? Absolutely!

Geoffrey James's recent article provides a succinct description of several important…

Steve Brown 1 Apr 2009 • less than a min read

DAC , Estimation Planning , TLM , RTL , System Design and Verification , Synthesis , ESL

Performance-Aware e Coding Guidelines - Part 1

[Team Specman welcomes back Methodology R&D leader Efrat Shneydor to present a 5…

teamspecman 1 Apr 2009 • 1 min read

IEEE 1647 , performance , IntelliGen , Specman , Functional Verification , tech tips , e , specman elite , Incisive Enterprise Simulator (IES) , IES-XL

Welcome to Richard Goering

Let me be among the first in the Cadence "blogger corps" to welcome Richard Goering…

tomacadence 31 Mar 2009 • less than a min read

Industry Insights , Functional Verification , EDA

Software Verification or Validation With ISX?

[Please welcome Markus Winterholer to the Team ESL blog. Markus is one of the founding…

TeamESL 30 Mar 2009 • 2 min read

validation , embedded world conference , System Design and Verification , ISX , ARM , verification

DVCon '09 SaaS Panel Thoughts, Part 3

In my previous posts on the DVCon 2009 panel on Software As A Service, or "SaaS"…

jvh3 30 Mar 2009 • 5 min read

SaaS , Functional Verification , Harry The ASIC Guy , DVcon , Xuropa

Is Software Engineering Engineering? You Decide!

Last night when I was waiting for my daughter to finish orchestra rehearsal (she…

jasona 27 Mar 2009 • 3 min read

System Design and Verification , failure tolerance , software engineering , design metrics

Moving Low Power Chip Design up to the System Level

Anybody watching Cadence these past couple years has probably noticed how we're pretty…

archive 24 Mar 2009 • 1 min read

System Design and Verification , Palladium , incyte , C-to-Silicon Compiler

Generation Action: Constraints From Above

[Welcome guest blogger Reuven Naveh of Specman R&D] What is the “constraints from…

teamspecman 24 Mar 2009 • 6 min read

IEEE 1647 , IntelliGen , Specman , Functional Verification , e , Aspect Oriented Programming , Incisive Enterprise Simulator (IES) , IES , AOP , IES-XL

Tracing TLM 2.0 Activity In An ESL Design – Part I

Many design teams that use SystemC are in various stages of evaluating TLM 2.0 –…

georgef 23 Mar 2009 • 6 min read

TLM , System Design and Verification , TLM 2.0 , SystemC analysis , George Frazier , sctlmrecord , ESL

Making the Right Decisions *Before* You Start Your Project

Seems logical, but unfortunately, I run into customers today that grumble about their…

Kenneth Chang 23 Mar 2009 • 3 min read

InCyte IP , chipestimate , System Design and Verification , chip estimation

Connecting OVM Testbench and SystemC TLM2 IP

1. Introduction With TLM2 enabling more sophisticated SystemC IP interoperability…

TeamESL 19 Mar 2009 • 9 min read

TLM2 IP , System Design and Verification , OVM , SystemC , testbench

C-to-Silicon Compiler Is The Only ESL Tool With ECO Capabilities

Another key differentiator of C-to-Silicon Compiler (CtoS) when compared to other…

TeamESL 19 Mar 2009 • 1 min read

ECO , CTOS , RTL , System Design and Verification , C-to-Silicon , ESL

IMPORT Guidelines For e, Part 1

[Team Specman welcomes AE Manager Avi Behar as our newest guest blogger] Hi, my name…

teamspecman 19 Mar 2009 • 4 min read

IntelliGen , Specman , Functional Verification , Avi Behar , OVM e , Register Package , e , OVM-e , specman elite , Aspect Oriented Programming , eRM , Incisive Enterprise Simulator (IES) , IES , AOP , IES-XL

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