Featured

Why LLMs Are the Best Thing to Happen to Chip Design

By Kartik Hegde, Sr. Engineering Group Director We live in a world increasingly…

Corporate
• 7 min read
featured , chip design , AGI , LLMs

Shift Verification Left: AI Tools for Faster, Smarter Chip Design

Originally written by Hamid Shojaei, Co-Founder of ChipStack and now Distinguished…

RobbieOSullivan
• 7 min read
ChipStack , featured , EDA , ChipStack AI Super Agent , AI

Cadence Welcomes VLAB Works

Cadence welcomes VLAB Works, a division of Australian Semiconductor Technology Corporation…

Corporate
• less than a min read
Automotive , featured , Virtual Development Environment , vlab , Protium
Verification
Latest blogs

Trip to SoCal "techtorials" on CDV

Just finished packing for a quick trip to Southern California to help kickoff a round…

• 1 min read
Functional Verification , Coverage-Driven Verification , CDV

Is anybody out there a Software Verification Engineer?

In my 2004 book, Co-Verification of Hardware and Software for ARM SoC Design , I…

• 3 min read
co-verification engineer , System Design and Verification , EDA

C-to-Silicon Compiler Launch

On July 14th, Cadence introduced C-to-Silicon Compiler, a next-generation high-level…

• 1 min read
high-level synthesis adoption , C-to-Silicon Compiler

Emulation Drivers - A growing set of selection criteria

Some say that the growth of the emulation market in last few years was driven by…

• 2 min read
Acceleration , System Design and Verification , Emulation , Hardware/software co-verification

The barriers to efficient System Level Design and Verification

The EDA industry been doing system level design and verification for years; we just…

• 1 min read
System Design and Verification

Verification Hierarchy of Needs

Verification consultant Brian Bailey recently started blogging for Chip Design Magazine…

• 2 min read
Verification planning and management , System Design and Verification , Run and Debug

The value of chaos (really!)

Ordinarily chaos is bad thing. Yet like it or not, t he world your SoC lives in is…

• 2 min read
Functional Verification

Why is OVM important for Specman/e customers?

With all of the press and interest from customers adopting it, I am sure most of…

• 2 min read
Verification methodology , Functional Verification , OVM , eRM

Report on the first OVM World Summit at DAC

At the recent Design Automation Conference (DAC) in Anaheim, Calif., Cadence did…

• 1 min read
DAC , Verification methodology , Functional Verification , OVM

'Verification Acceleration' vs. 'Simulation Acceleration'

Simulation acceleration and emulation technology has been commonly used to run faster…

Anonymous • 1 min read
Acceleration , System Design and Verification , Emulation , Verification Acceleration , Simulation acceleration

ESL handoff: closer than you think

Take a look at the article linked below, titled: "ESL handoff: closer than you think…

• less than a min read
System Design and Verification , ESL handoff

Dreaming in Code

One of the best books I read this year is called Dreaming in Code by Scott Rosenberg…

• 2 min read
Dreaming in Code , System Design and Verification , Chandler project

Do you want to buy my chip?

Once upon a time semiconductor companies produced a chip, made a data sheet, showed…

• 1 min read
System Design and Verification , Hardware/software co-verification
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