Featured

Why LLMs Are the Best Thing to Happen to Chip Design

By Kartik Hegde, Sr. Engineering Group Director We live in a world increasingly…

Corporate
• 7 min read
featured , chip design , AGI , LLMs

Shift Verification Left: AI Tools for Faster, Smarter Chip Design

Originally written by Hamid Shojaei, Co-Founder of ChipStack and now Distinguished…

RobbieOSullivan
• 7 min read
ChipStack , featured , EDA , ChipStack AI Super Agent , AI

Cadence Welcomes VLAB Works

Cadence welcomes VLAB Works, a division of Australian Semiconductor Technology Corporation…

Corporate
• less than a min read
Automotive , featured , Virtual Development Environment , vlab , Protium
Verification
Latest blogs

Embedded Software Bugging and Debugging

In one of my previous posts I introduced an interesting book titled Dreaming in Code…

• 4 min read
bugging and debugging' , System Design and Verification , embedded software

Getting more value from the OVM using Metric-Driven Verification

With all of the momentum around the OVM these days there has been a lot of good discussion…

• 2 min read
SystemVerilog , Verification methodology , metric driven verification (MDV) , Functional Verification , Open Verification Methodology , Testbench simulation , OVM , Coverage-Driven Verification , CDV , Enterprise Manager , coverage driven verification (CDV) , eRM

Verification community comes together to talk tech

I just finished the week at Cadence's CDNLive User Group in San Jose. Over the past…

• 1 min read
SystemVerilog , Verification methodology , CDNLive , metric driven verification (MDV) , Functional Verification , CDNLive San Jose 2008 , Formal Analysis , Open Verification Methodology , Testbench simulation , OVM , Coverage-Driven Verification , CDV , Enterprise Manager , ISX (Incisive Software Extensions) , Simulation acceleration , coverage driven verification (CDV) , ISX , eRM , System Verification

A few thoughts on CDNLive! and OVM 2.0

My colleague Joe Hupcey has been keeping you informed and entertained with information…

• 1 min read
CDNLive San Jose 2008 , OVM 2.0

OVM 2.0 -- Short Technical Review

By now you may have seen the official announcement of the OVM 2.0 release . So what…

• 3 min read
SystemVerilog , Verification methodology , OVM , CDV , System Verification , OVM 2.0

Day 3 of CDNLive San Jose

Highlights of Day 3: papers all morning, lunch, then closing remarks. Comments on…

• less than a min read
verification strategy , Verification methodology , CDNLive , metric driven verification (MDV) , Functional Verification , CDNLive San Jose 2008 , Multi-domain verification: HW/SW co-verification , Enterprise Manager , ISX (Incisive Software Extensions) , Plan and metrics management , Verification IP modeling , ISX

Day 2 of CDNLive San Jose 2008

Highlights of Day 2: more great papers (with enough customer papers on OVM fill almost…

• less than a min read

Day 1 of CDNLive San Jose 2008

Suffice to say, Day 1 was quite a full day, with the highlight for me being some…

• less than a min read
AMS , CDNLive San Jose 2008 , Multi-domain verification: HW/SW co-verification , multi-language

Enterprise Verification gets a boost (a big one!)

Today we announced important new metric-driven verification capabilities in our enterprise…

• less than a min read
Verification methodology , CDNLive , metric driven verification (MDV) , Functional Verification , Formal Analysis , Coverage-Driven Verification , CDV , Enterprise Manager , Plan and metrics management , coverage driven verification (CDV) , IES

"Day 0" of CDNLive San Jose 2008

Quick report from CDNLive Day 0 (I've labeled it that since this initial day was…

• 1 min read
CDNLive San Jose 2008 , MDV techtorial , System Verification

CDNLive SJ - system design and verification - don't miss it

If you are a system validation/verification engineer, an architect, a power engineer…

• 1 min read
Low Power , power engineer , system validation/verification engineer , embedded SW engineer , architect

See you at CDNLive San Jose next week

FYI, Mike Stellfox and I will be at CDNLive San Jose next week. In addition to reporting…

• less than a min read
Functional Verification , OVM , ISX (Incisive Software Extensions) , IES

Chip Level Verification with Processors

Today, I will discuss some alternatives for chip-level verification with designs…

• 6 min read
verification strategy , Functional Verification , ISX , ARM , FPGA: DMA

The Road to Better Software Verification

It seems the debate over the benefits of better software verification is still alive…

• 5 min read
Intel , Specman , System Design and Verification , Frank Schirrmeister

ESL: The state of the industry and what’s next?

While ESL continues to remain in its infancy, there are signs within the industry…

• less than a min read
System Design and Verification , ASIC/ASSP , advanced process nodes , ESL

Experiences on Marketing a Verification Library

Inspired by JL Gray of the blog "Cool Verification" who stated, in this post: "I…

• 2 min read

Embedded Systems Conference Boston 2008

Friday is that last day to get the Early Bird price for the Embedded Systems Conference…

• 1 min read
System Design and Verification , Coverage Driven Verification for Embedded Software , Embedded Systems Conference 2008 , debugging , Jason Andrews , verification

iPhone 3G issues - result of HW/SW-co-verification?

In a recent article at cnet, financial analyst said he believes Apple's iPhone 3G…

• 2 min read
Richard Windsor , Infineon 3G chipset , Infineon , System Design and Verification , iPhone 3G , Nomura

ESL gets a new taker

Interesting High-Level Synthesis review by Bryon Moyer at IC Design and Verification…

• less than a min read
High-Level Synthesis , IC Design and Verification , CDNLive! Silicon Valley 2008

Is Concurrent Engineering actually getting worse?

Today I'm taking a few minutes to jot down a few recent observations about the state…

• 3 min read
Concurrent Engineering , System Design and Verification , ISX

OVM - The Methodology for Enabling an Industry-wide VIP Eco-System

As the leader of the Cadence OVM development team, I was reading Richard Goering…

• 3 min read
SystemVerilog , OVM Professionals Network , Verification methodology , Functional Verification , Open Verification Methodology , OVM , Verification IP modeling , eRM , OVMWorld

OVM Leaves the Nest

OK JL , one more marketing post, but this is a good one and even hints at technical…

• less than a min read
Functional Verification , OAG , OVM , OVM Advisory Group , OVMWorld

Putting a face on the OVM

As I recently blogged , there appears to be growing buzz over the Open Verification…

• 1 min read
CDNLive , Open Verification Methodology , OVM

Design space exploration

In his latest blog post Space Exploration ... design is , Grant Martin said that…

• 1 min read
high-level synthesis adoption , System Design and Verification , C-to-Silicon Compiler

Report from the CDV techtorials in SoCal

To follow-up on my previous post on the techtorials, I'm posting some photos from…

• 1 min read
metric driven verification (MDV) , Functional Verification , OVM , coverage driven verification (CDV) , eRM

Flexibility Often Yields Unexpected Results

Often, when engineers set out to build something, the result is different from the…

• 4 min read
Functional Verification , Founders at Work Stories of Startups' Early Days , ISX (Incisive Software Extensions)

OVM is "Open" for Business

Open things are just curiosities until the ecosystem figures out how to turn them…

• 1 min read
SystemVerilog , OVM Professionals Network , Functional Verification , Testbench simulation , OVM , OVMWorld

Transaction-Based Acceleration - Second generation

Transaction-Based Acceleration is becoming more and more important as an extension…

• less than a min read
System Design and Verification
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