IC Packaging and SiP Blogs

Design reuse is the key to faster design cycles in today’s packaging design industry, where the shortest possible time to market makes or breaks the success of a product. As most of the package designs have wire bonding, sharing the wire bondin...

In today's ever-shrinking IC Package design cycles, it is almost imperative that we catch and correct routing issues as early as possible, which makes simulation an integral part of the design cycle. Layout engineers want a quick and accurate way to ...

The task of IC/package co-design causes multiple challenges during the design cycle and one of them is to update the netlist of co-design die or BGA in the middle of the design cycle. The current process of updating connectivity provides no flexibili...

Let’s focus today on an established routing technology with a new twist! All of you are doubtless familiar with the concept of structures – formerly called via structures, renamed to structures because of their growing flexibility and application across many flows.

All of you doing advanced node package or silicon interposer substrate design in Allegro® Package Designer know what degassing is. And, while we talked last summer about massive performance improvements (plus additional information in show elemen...

I could doubtless extend this series all year long, covering the important updates, improvements, and completely new functionality that is continually being added to the Allegro® Package Designer product. This will be my last before we shift back...

As promised, we’re back with some more of the big improvements that are part of the QIR2 update release of 17.4 (HotFix 013). This time, everything is specific to our Allegro® Package Designer Plus community. Without further ado, then, let&...

Welcome to a brand-new year, everyone! As we welcome in 2021, we also welcome the next major update to the 17.4 Allegro platform release in the form of QIR2 (hotfix 13). These new updates are exciting for many reasons. Of course, they bring bug fixes...

And so, here we are at the end of the year. I do hope that our weekly IC posts livened up 2020's groundhog days full of online meetings, washing up, and frantic searches for an Icelandic crime series you haven't yet watched! As we take stock ...

Some items are useless on multiple levels. The most common multi-class pairing is probably the package substrate outline and the route/component keep-in shapes. Since it’s unwise to route or place anything off the edge of the world, it is impor...

ECOs. Without them, the lives of designers would be so much easier! Imagine a world where the original requirements you were given never changed throughout the design. Unfortunately, such a world, as we know, does not exist. How, then, can you track ...

Are you like me? Do you forget things and have a running to-do list for your designs? Would you like to leave instructions and comments for your colleagues to remind them of actions needing doing? There are many places to record this type of informat...

More package designers these days, with the increasing component counts and more complicated electrical constraints, are shifting to using a front-end schematic capture tool. As with IC and PCB design, this allows for verification between the logical...

Back at the start of 2020, we talked about why you shouldn't use the default wire profile in your actual design. Today, I want to take this a step further. If you do wire bond designs, you are doubtless aware of the certified bond wire profiles t...

Let’s investigate this question today, as I’ve been asked a few times over the years by curious designers. The question is one of wanting to start from the Allegro Package Designer environment and begin prototyping a die pin layout. If yo...

Many of you out there are SKILL coders (or have these people on your team). SKILL is the extension programming language for all the backend layout products in the Allegro family, including Allegro Package Designer. If you’ve read up on the blog...

Hello, all. As we push towards the next major update to the 17.4 release, the team here at Cadence is very busy! We hope you’ll be as excited by the new updates, enhancements, and bug fixes as we are. But until then, there is still plenty of ca...

With greater and greater counts of high-speed and differential pair signals in designs, the ability to control the areas around these nets becomes more important. Adjusting and maintaining the distance to these nets on the same layer as the routing i...

When you are placing components (or defining your BGA pattern), often it is necessary to escape each of those pins to a given internal layer. This could be to get your power and ground supply to the designated plane layer. Or, it might be the first s...

Soldermask and its brethren are stable in the EDA design industry. These layers control what is exposed to the elements (and to electrical connections!) on the top and bottom layers of the substrate. But, for many years, they have been a part of the ...

When you send the initial version of your design for manufacturing, it’s a huge sense of accomplishment. Things are complete. All constraints have been met. When the part comes off the manufacturing line, it works. That is something to be proud...

It may surprise some of you, but I often receive databases in which the power and ground nets are not properly identified. Many times, I get these with questions about slow performance during editing actions in the design or a basic confusion of why ...

When you are creating a BGA package component, you are, almost certainly, going to be implementing one that adheres to JEDEC standards. This means selecting from a set of available package size and pin pitch combinations, using a specific, grid-based...

There are many reasons a die’s size in the package doesn’t match the design size recorded in the IC layout tool. For starters, the IC layout doesn’t always include the scribe lines and other manufacturing offsets/adjustments that do...

We’ve covered all the different types of die components and how they interface with the package substrate coming into Allegro Package Designer. But, the package component (whether it’s a BGA, LGA, lead frame, or something else) is destine...