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Reports – Now Sorting Your Strings the Way YOU Want Them Sorted

By IC Packaging Pros | 25 Mar 2016

When it comes right down to it, if we asked most of you what was the most important feature to you, many would probably answer with things like routing, wire bonding, net assignment optimization, or DRC checks. All great responses, and each of them a very important functional area in its own right. But, if you pick up the latest 16.6 ISR release, you will notice a subtle change that may just have a larger impact on...

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documentation | Cadence Design Systems | Reports | manufacturing exports | APD | Allegro Package Designer | IC packaging documentation | SiP Layout | sorting
Designing a New Component from Scratch Inside Your Layout Environment

By IC Packaging Pros | 11 Mar 2016

Have you ever needed to build a component with a custom, complex pin pattern? Have you ever wanted to do so within the context of the substrate you’re working on (or, for that matter, needed to build a custom package based on a set of dies you need packaged)? You might not realize it, but you can do this within the SiP Layout and Allegro Package Designer L environments. There is no need to first bring in a base...

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IC package design | APD | package design | Allegro Package Designer | SiP Layout | substrate design tools
How to Overlay Shapes on Top of Sets of Reference Objects with the Latest Cadence IC Packaging Tools

By IC Packaging Pros | 22 Feb 2016

Many of you are familiar with the bond finger soldermask opening creation tool—used for years, it allows you to create a single, smooth hole in your soldermask shapes that exposes all the bond fingers in a single row of fingers. Rather than having indents and sharp edges that can peel away, creating a simple opening allows for improved manufacturing and a cleaner overall design. But, did you know that you can...

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bounding shapes | SiP | IC package design | APD | beta tools | package design | shapes
How to Maximize Performance When Your Package Layout Gets Complicated

By IC Packaging Pros | 5 Feb 2016

We are all familiar with it. Every year, designs get faster, smaller, and more complicated. Whether your newest package has a towering stack of memory dies placed into a cavity or a few massive flip-chips with critical bus lanes between them, it never fails. The database that represents that complex package is, itself, growing more complex. Co-design dies, flow planning bundles, via structures for fan out and shielding...

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Cadence Design Systems | SiP | Digital SiP design | IC package design | APD | package design | Allegro Package Designer
Customize the Organization of Bond Wires in Your Artwork Films with SiP Layout and Allegro Package Designer

By IC Packaging Pros | 15 Jan 2016

When it comes to IC Package substrates, Gerber is still one of the most common, most popular formats used to send the design for manufacturing. Being a strictly 2D format, however, how do you best fit bond wires into your artwork films if you want to be able to see them? The same wire profile can connect pins from multiple dies to the substrate, to each other, or can even connect one die pad on the top and another...

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SiP | Allegro package design | Digital SiP design | IC package design | APD | package design | manufacturing | wirebonding | substrate design tools
Take Tighter Control Over Your Shape Degassing Patterns with Cadence 16.6 Allegro Package Designer and SiP Layout

By IC Packaging Pros | 30 Nov 2015

With metal density and balancing requirements getting stricter with every year that passes, how you perforate the plane shapes of your designs needs to adapt. Whether it is a new hole shape that allows for a more consistent pattern fill across the layer, multiple passes with progressively smaller holes to achieve that optimal balancing of metal, or perhaps a complex interplay of holes on neighboring layers in your...

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Cadence Design Systems | SiP Design | 16.6 | IC package design | APD | Allegro Package Designer | manufacturing | SiP Layout | shapes
Generate Daisy Chain Patterns for Test Vehicles and Other Applications Using the Cadence SiP Layout 16.6 June 2015 Update

By IC Packaging Pros | 11 Sep 2015

With increasing design complexity comes the need to create test vehicles to qualify new processes and ensure that the substrates will be able to tolerate the expected wear and tear, long term load, and other situations that may not fall under the umbrella of “ideal conditions.” To that end, creating a daisy chain version of your substrate that can be used for reliability testing purposes is becoming a standard...

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Co-Design | 16.6 | manufacturing | early adopter | SiP Layout | substrate design tools | Physical layout and co-design | daisy chain
Integrate PVS into Your IC Package Design Flow to Optimize for Manufacturability with Latest 16.6 ISR of Cadence SiP Layout

By IC Packaging Pros | 28 Aug 2015

As package substrates continue to get more complex, often resembling silicon as much as traditional organic substrate, design rules get tighter, manufacturing concerns become more important, and the simple act of ensuring that high yield, high reliability is a fact of life that becomes anything BUT simple. The APD and SIP Layout tools provide a robust set of online DRC checks around spacing and physical characteristics...

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IC Packaging and SiP Design | GDSII | DRC | stream | 16.6 | SPB | PVS
Manage Your Shapes with Ease in the Latest 16.6 ISR of Cadence APD and SiP Layout

By IC Packaging Pros | 5 Aug 2015

Shapes. Whether it’s a split plane, a power ring or flag under your die, or a cavity outline, they abound in any IC package substrate. Some are filled, others cross-hatched or even degassed. Whatever they look like in your design, editing them can cut into the time you spend to get your substrate perfected. That is why, with the latest June 2015 update release of 16.6, we are bringing you a number of exciting...

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IC Packaging and SiP Design | Cadence Design Systems | bounding shapes | Digital SiP design | degassing | 16.6 | beta tools | package design | SiP Layout | shapes | application modes
BGA Ball Map Creation

By TeamAllegro | 6 Jul 2015

Are you responsible for the creation and management of a BGA ball map or a die bump map of a packaged chip design? How much time do you spend creating these maps? How do these maps drive physical implementation in your design? It’s common for most companies to use spreadsheets to create the ball map or die bump map of a chip, and if you do, you know how tedious, time consuming, and error prone a process it is. On...

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Co-Design | IC package design | I/O planning | BGA ball map
Designing a Complex Leadframe Package? See How SiP Layout Tool Can Cover All the Steps

By IC Packaging Pros | 2 Jul 2015

Leadframe package designs are here to stay, and they are getting more complex with every passing year. New materials and manufacturing processes allow for the inclusion of more active and passive components, while new bonding capabilities stretch the available pin counts. At the same time, signal, power, and thermal integrity challenges continue to mount. Simple designs, which could previously be done inside of a mechanical...

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IC Packaging and SiP Design | Cadence Design Systems | leadframe | SiP | Digital SiP design | design variants | IC package design | package design | SiP Layout | wirebonding
Manage All Design Variant Options for Your Package Substrate Seamlessly Using 16.6 Cadence SiP Layout

By IC Packaging Pros | 18 Jun 2015

Stacked memory is becoming increasingly common in IC package substrates; with that memory being sourced from multiple vendors, managing all the different combinations of your logic die(s), memory components, controllers, and BGAs in a way that your package functions properly in all configurations while still minimizing the per-unit cost gets harder with each new generation of substrates. Pick up a copy of the 16.6...

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IC Packaging and SiP Design | stacked dies | SiP | IC Package | IC Packaging | SiP Design | design variants | package design | SiP Layout
Optimize Complex Net Assignments Faster than Ever with Split Views in Cadence APD and SiP Layout

By Jeff Gallagher | 20 Feb 2015

More differential pairs, larger buses, denser pin arrays… it’s no secret that IC package designs are getting more complex with each passing season. The Cadence IC Package layout tools provide many tools for helping you overcome all of these hurdles. Flow bundles, automatic net assignment/optimization tools, and interactive and batch pin swapping tools – whatever stage you are at, there is a tool to...

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SiP | IC Package | IC Packaging | Allegro package design | SiP Design | Digital SiP design | IC Packaging and SiP | APD | IC Packaging & SiP design
Do You Design Wafer-Level Chip-Scale Packages? Cadence 16.6 SiP Layout Makes Your Job Easier!

By Jeff Gallagher | 6 Nov 2014

As these types of designs see an increasing number of applications and design starts, we need tools that make it as easy and efficient as possible to turn them from a specification to a finished layout. Whether you get seed information in GDSII, DXF, artwork, or another format, you need tools to turn raw geometry objects into an intelligent layout, apply technology rules, constraints, and a netlist, and then complete...

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IC Package | SiP Design | Co-Design | layout pin numbering
Have a Complex, Off-Grid Pin Pattern to Number? Cadence Allegro16.6 IC Package Design Tools Have You Covered!

By Jeff Gallagher | 5 Sep 2014

Complex dies with a mixture of digital and analog circuitry means equally complex pin patterns. Those analog areas often have pins that aren't lined up in nice, straight rows and columns. But, that doesn't mean that the pins don't still need a defined pin-numbering pattern. What do you do in this case to get the pin numbers just the way you want them? With Cadence Allegro Package Designer and SiP Layout XL...

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IC Packaging and SiP Design | IC Packaging | IC packaging SiP Layout | SiP Design | Digital SiP design | IC Packaging and SiP | layout pin numbering | IC packaging documentation | pin numbering | SiP Layout
Strengthen Your Plane-to-Plane Connections with Cadence 16.6 IC Package Shorting Via Arrays

By Jeff Gallagher | 31 Jul 2014

Manufacturability and quality of the power and ground feeds for your package are always a big concern for all of us. When you have multiple plane layers, connecting them together with reinforcing vias is a great idea, with just one problem: how do you figure out where to put them that won't conflict with anything connected to the planes—or anything on the layers between them? This connection can be a very...

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SiP | IC Package | 16.6 | APD | package design | Allegro Package Designer
Build Components Quickly and Easily with Pre-Defined Escape Routing Using Cadence 16.6 IC Packaging Tools

By Jeff Gallagher | 2 Jun 2014

When it comes to designing a dense flip-chip die - or even defining a BGA for a complex substrate - the ability to efficiently fan out the pins in the fewest possible layers is paramount. Get this wrong, and you could end up needing additional layers in your package substrate, which will cut into your profits on each and every produced component. It is safe to say that is something that we universally want to avoid! ...

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Allegro package design | reusable tiles | EDA | package design | SiP Layout | substrate design tools
Add a View of Your Package Substrate in Your IC Layout Tool for Maximum Design Context with Cadence 16.6 SiP Layout

By Jeff Gallagher | 1 May 2014

We have all heard about co-design, how it is going to get us to market on time, reduce our layer counts, and give us the ability to trade off design decisions at different layers of the system substrates. If you're reading this blog, you almost certainly know about the co-design capabilities present in the Cadence SiP Layout tools—features that allow you to "see into" the IC substrate to the driver...

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SiP | Allegro Package Designer | IC packaging documentation | APD 16.6 | SiP Layout
OrbitIO/SIP-XL Co-Design Flow Highlighted at CDNLive SV 2014

By TeamAllegro | 8 Apr 2014

The Cadence user group event in Silicon Valley, CDNLive SV 2014, had a number of different focused topic tracks at the event. (See the complete two-day agenda .) Track 6, IC Packaging/SI, PI, featured customer papers on co-design as well as signal and power integrity. With the growing challenges of planning and implementing the latest generation of multi-gigabit parallel bus interfaces like DDR3 or DDR4, it's...

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SiP | DDR interface | CDNLive | Co-Design | IC package design | OrbitIO
Cadence Sigrity Full-Wave 3D Field Solver Technology Highlighted at CDNLive SV 2014

By TeamAllegro | 28 Mar 2014

The Cadence user group event in Silicon Valley, CDNLive SV 2014, had a number of different focused topic tracks at the event. For the complete two day agenda, click here . Track 6, the IC Packaging/SI, PI featured customer papers on co-design as well as signal and power integrity. With the challenges of faster speeds, denser designs, and lower product costs permeating the electronics industry, it is easy to understand...

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single and multi-fabric design | full wave 3D field solver | power integrity | IC package design | 3DEM | signal integrity
Balance Metal Coverage Across Different Layers with Ease Using Cadence 16.6 IC Packaging Layout Tools

By Jeff Gallagher | 26 Mar 2014

To maximize yield and achieve optimum quality of your final, manufactured IC package substrate, we all want to balance the metal coverage across different layer - and region - pairings of your package layout. But, just how do you go about doing that with your package design tool? With the 16.6 release of Cadence Allegro Package Designer and SiP Layout tools, you can be well on your way to achieving fantastic results...

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IC Packaging and SiP Design | SiP | IC Package | IC Packaging and SiP | IC package design | IC Packaging & SiP design | IC packaging documentation | substrate | SiP Layout
Customize Your Menus Dynamically with SKILL in Cadence Allegro 16.6-Based Layout Editors

By Jeff Gallagher | 5 Mar 2014

Many users of the Allegro, APD, and SiP tools are familiar with the great flexibility that allows them to extend and modify the tool to meet their specific requirements. This might mean custom SKILL tools developed in-house, scripts/macros to automate repetitive tasks, or the integration of third-party tools. Whatever scenarios you may use, it is normally desirable to place these extensions in the tool menus. Doing...

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IC Packaging and SiP Design | IC packaging SiP Layout | Digital SiP design | IC Packaging & SiP design | IC packaging documentation | IC Package Physical layout and co-design
Improve Design Quality with Adjacent Layer Object Avoidance in the 16.6 Cadence APD and SiP Layout Tool

By Jeff Gallagher | 13 Feb 2014

In this week's discussion, let's take a look at a cornerstone of every good substrate design: plane shapes and voiding. In particular, what do you do if you need to void around an object on one or more layers of the object itself, whether a cline, via, bond finger, or pin, does NOT itself exist? There are many reasons for needing to do this. You may want to ensure that a high-speed signal has no interference...

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IC Packaging and SiP Design | package | packaging | IC Packaging and SiP | APD | IC Packaging & SiP design | SiP Layout | IC Package Physical layout and co-design
See the Differences Between Your Designs Visually with the Layer Compare Toolset in 16.6 APD and SiP Layout Tools

By Jeff Gallagher | 15 Jan 2014

Have you ever wondered exactly what has changed between two different versions of a package substrate? Perhaps you've wanted to see exactly what metal on the top surface of your package is exposed through the combination of solder mask openings and etch-back mask areas. Or, it could be that a metal density analysis across two layers shows significant differences and you want to see all the areas where only one of...

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IC Packaging | solder mask layer | substrate | SiP Layout | layer compare tools
Take Your Via Structures from Ordinary to Exceptional with 16.6 IC Packaging Advanced Commands

By Jeff Gallagher | 5 Dec 2013

Via structures—those reusable patterns of conductor clines and vias designers rely on to maximize their productivity—have a long-standing place in the robust escape routing feature set in the Cadence IC Packaging Tools. Many of us use only the basic capabilities in the via structures repertoire, though, to create structures in the current drawing and replicate them across a pattern of pins. Today...

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IC Packaging and SiP Design | SiP | IC Packaging | packaging | Analog and RF SiP design | 16.6 | IC package design | APD | wirebonds | APR | IC Packaging & SiP design | BGA | Allegro Package Designer | IC packaging documentation | early adopter | APD 16.6 | SiP Layout | wirebonding | IC Package Physical layout and co-design

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