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IC Packagers: A Cross-Section of Changes

By Tyler | 19 Nov 2019

While 17.4 has only been amongst you for a month, now, I’ve had a few questions regarding manipulating your layer stack-up in the new release. We covered scripting changes previously, but a quick chat about the general use model is warranted. T...

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APD
IC Packagers: Plan Your Escape with Modernized Structures

By Tyler | 12 Nov 2019

Many of you, our regular readers, are familiar with via structures. These reusable patterns of vias, clines, shape, and keep-out shapes, and return path elements allow you to escape a single pin then replicate that structure (or pattern of structures...

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17.4 | APD
IC Packagers: Scripting Updates in 17.4

By Tyler | 6 Nov 2019

If you joined us last week to see the visual changes to be expected when you download 17.4, doubtless the next thing you need to know is how migrating will impact your automation. And, if you’ve installed the software already, you’re one ...

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APD | PCB Editor
IC Packagers: Welcome to 17.4!

By Tyler | 30 Oct 2019

It’s here! Less than two weeks ago, on October 18, 2019, Cadence released the 17.4-2019 version of the Allegro product line. This means exciting new features, enhancements, bug fixes, and performance improvements to the tools you depend on to d...

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17.4 | APD
IC Packagers: Manage Your Outside Data Sources in One Place

By Tyler | 22 Oct 2019

Every package design has data sources. Die data you receive from the IC design team as they send you updated die text files and co-design die abstracts. Your downstream PCB design team may send an updated ball map spreadsheet with change requests. Obviously, your front-end schematic engineer will be pushing you updated netlist information. How do you keep track of when the last time was that you imported data from a...

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APD | PCB Editor | SiP Layout
IC Packagers: Optimize Display Settings for Faster Screen Redraws

By Tyler | 15 Oct 2019

While designing interposers and very high pin count device packages, as the number of objects to manipulate increases, you may notice that the display takes longer to draw. This is for a very good reason: by default, the tools will draw everything.....

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PCB | APD | SiP Layout
IC Packagers: Undoing Your Custom SKILL Commands

By Tyler | 8 Oct 2019

Today, we’ll talk about something simple but still important. For all of you who write your own SKILL code commands to help your teams be more productive, this one’s for you. Any time you are modifying the database, it is important that y...

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APD | SiP Layout | SKILL
IC Packagers: Wrap Your Hands Around a Coil

By Tyler | 1 Oct 2019

Coils are a design element that, if not exceedingly common, are showing up in more designs these days. They appear simple at first glance, but keeping a consistent air gap between each revolution of the spiral can involve a lot of mental arithmetic and picks in the design canvas. Here's how to do this with a few short clicks?

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SiP Layout
IC Packagers: Finding Design Issues in SiP - Three Options for DRC Management During Sign Off

By Tyler | 24 Sep 2019

Your design is complete. Yet, you have 20 DRC violations that need to be addressed (whether that means correcting the constraint required value, modifying objects, or waiving the DRC to sign off on it as okay). What’s the best way to go about r...

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APD | SiP Layout
IC Packagers: Capture Your Design for Review

By Tyler | 17 Sep 2019

How do you quickly show another developer an issue that concerns you? Do you need to send them the entire design, start a screen sharing session, or bring up the Symphony server and allow them to connect? All of these are GREAT review mechanisms; however, they aren’t always viable or convenient.

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APD | SiP Layout
IC Packagers: How Far Away are You?

By Tyler | 10 Sep 2019

Layout design is all about clearances. Daily challenges come from maintaining consistent space between your differential pair members, calculating the number of routing channels you can squeeze between two vias, or ensuring adequate clearance of bond...

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SiP Layout
IC Packagers: Manufacturing Cross-Hatched Shapes

By Tyler | 3 Sep 2019

If you use cross-hatched shapes in your package design, you are doubtless aware of some considerations. Namely, if your shape outline is anything but a rectangular outline at a multiple of the hatch line width pattern, and unless it has no objects to...

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SiP Layout
IC Packagers: Rule Your Package Designs

By Tyler | 27 Aug 2019

When it comes to package design, spacing often reigns supreme. The location readout in the bottom status bar of the tool will always tell you where your cursor is in the design; this can show either absolute or relative mode (in which case coordinate...

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SiP Layout
IC Packagers: Choosing the Right Netlist to Match Your Needs

By Tyler | 20 Aug 2019

Netlists. Everyone needs them! But what you are using your netlist for can have a significant influence on just what KIND of netlist you want. Fortunately, the Cadence SiP tools offer formats for just about every situation you might run into, from in...

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APD | IC Packaging & SiP design | SiP Layout
IC Packagers: Grouping Items with Symbol Instances

By Tyler | 13 Aug 2019

Whether you’re adding lines, text, shapes, routing elements, or any other feature to the design, most elements assume that you are placing them at the design level. If they are part of the symbol, they would be part of the library object. Is there a quick and convenient way to take the additional elements and assign them to the placed symbols in your design so that everything stays together in easy to manipulate pieces...

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IC Packaging | SiP Layout
IC Packagers: Six Steps of IC Packaging

By mrigashira | 6 Aug 2019

Do you want to create an IC Package and are on the lookout for a tool that suits you? Or, you might already be using APD or SiP Layout but want to know their full potential. We will talk about six broad steps of IC Packaging and how APD and SiP Layout make the steps efficient and easy for you.

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APD | IC Packaging & SiP design | SiP Layout
IC Packagers: Multi-Wire Bonding with Ease Using Cadence IC Packaging Tools

By Tyler | 31 Jul 2019

When wire bonding, the most common situation remains a single wire from pin to finger. There may be die to die connections as you step down from one die to the next in a stacked die situation (sometimes called a stitch bond, where the wire is tacked ...

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APD | wirebonds | SiP Layout
IC Packagers: Correcting Die Orientations and Die Attachments

By Tyler | 23 Jul 2019

When you add a die component to your SiP Layout design, you must identify both its default attachment type – wire bond or flip-chip – and its orientation – chip up or down. But, what happens if you get this wrong? The most common re...

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APD | SiP Layout
IC Packagers: Bend in Both Directions with J-Loop Bond Wires

By Tyler | 16 Jul 2019

Let’s talk about wire bonding for a quick minute. Still a favorite for many of you, bonding is a cheap way to connect your die to the top layer of your package (or to a lead frame, if that’s what you’re using). A 3D wire is connecte...

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IC Packaging | APD | SiP Layout
IC Packagers: Balance Your Designs with Cadence SiP Layout

By Tyler | 9 Jul 2019

As designs get more complicated, package substrates are seeing more silicon-driven rules and structures. Substrate styles like fan-out wafer level packaging (FOWLP) and elements such as through-silicon vias (TSVs) being injected into the package lay...

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IC Packaging | APD | SiP Layout
IC Packagers: Vary Your Assembled Packages, Not Your Databases

By Tyler | 3 Jul 2019

Design variants are a common phenomenon, whether you design package substrates or PCBs. You may source a resistor from multiple vendors, and part of the design flow includes generating a bill of materials (BoM) which lists all the parts that go on a ...

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IC Packaging | APD | SiP Layout
IC Packagers: The Spaces Between Your Dies

By Tyler | 25 Jun 2019

Die stacks are starting to look more like skyscrapers every year. If your packages involved vertical stacks of components of any kind, then you know there is more involved in stacking your dies than just the components themselves. What about interpos...

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IC Packaging | APD | SiP Layout
IC Packagers: Constructing Components from Manufacturing Data

By Tyler | 20 Jun 2019

We’ve all been there. The only (or most accurate) data that we have for a component is the manufacturing data from another process. It could be a GDSII file for the top-layer metal of an IC or a Gerber film for the BGA ball pattern. If all you ...

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IC Packaging and SiP | APD | SiP Layout
IC Packagers: A Classic Revisited - Ball Map Spreadsheets

By Tyler | 11 Jun 2019

Interfaces to the major spreadsheet commands from OpenOffice, Microsoft, Google, and others are becoming more common in EDA, Cadence® SiP has had a great interface since early in the 16.6 release. You, our users, continue to find creative new use...

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APD | SiP Layout
IC Packagers: The (Copper) Pillars of Modern Design

By Tyler | 4 Jun 2019

Wire bonding has been around forever. Flip-chip mounting? That’s been around for a long time as well. Every new generation of packages brings with it new technologies, challenges, and options. Copper pillars have been around for a fair time as ...

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IC Packaging | IC Packaging and SiP | SiP Layout

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