IC Packaging and SiP Blogs

More package designers these days, with the increasing component counts and more complicated electrical constraints, are shifting to using a front-end schematic capture tool. As with IC and PCB design, this allows for verification between the logical...

Back at the start of 2020, we talked about why you shouldn't use the default wire profile in your actual design. Today, I want to take this a step further. If you do wire bond designs, you are doubtless aware of the certified bond wire profiles t...

Let’s investigate this question today, as I’ve been asked a few times over the years by curious designers. The question is one of wanting to start from the Allegro Package Designer environment and begin prototyping a die pin layout. If yo...

Many of you out there are SKILL coders (or have these people on your team). SKILL is the extension programming language for all the backend layout products in the Allegro family, including Allegro Package Designer. If you’ve read up on the blog...

Hello, all. As we push towards the next major update to the 17.4 release, the team here at Cadence is very busy! We hope you’ll be as excited by the new updates, enhancements, and bug fixes as we are. But until then, there is still plenty of ca...

With greater and greater counts of high-speed and differential pair signals in designs, the ability to control the areas around these nets becomes more important. Adjusting and maintaining the distance to these nets on the same layer as the routing i...

When you are placing components (or defining your BGA pattern), often it is necessary to escape each of those pins to a given internal layer. This could be to get your power and ground supply to the designated plane layer. Or, it might be the first s...

Soldermask and its brethren are stable in the EDA design industry. These layers control what is exposed to the elements (and to electrical connections!) on the top and bottom layers of the substrate. But, for many years, they have been a part of the ...

When you send the initial version of your design for manufacturing, it’s a huge sense of accomplishment. Things are complete. All constraints have been met. When the part comes off the manufacturing line, it works. That is something to be proud...

It may surprise some of you, but I often receive databases in which the power and ground nets are not properly identified. Many times, I get these with questions about slow performance during editing actions in the design or a basic confusion of why ...

When you are creating a BGA package component, you are, almost certainly, going to be implementing one that adheres to JEDEC standards. This means selecting from a set of available package size and pin pitch combinations, using a specific, grid-based...

There are many reasons a die’s size in the package doesn’t match the design size recorded in the IC layout tool. For starters, the IC layout doesn’t always include the scribe lines and other manufacturing offsets/adjustments that do...

We’ve covered all the different types of die components and how they interface with the package substrate coming into Allegro Package Designer. But, the package component (whether it’s a BGA, LGA, lead frame, or something else) is destine...

Recently, we’ve covered some basics about why imported dies default to chip-down flip-chips and even the different types of mirroring . To close on the topic of dies, die stacks, and the interaction of components why may interface together witho...

The BGA component serves the primary role of redistributing the signals from the die it protects to an interface pattern (the BGA’s balls) compatible with the host PCB it mounts on. As a result, many IC package designs are among those who do no...

Most package substrates are designed as they will be placed onto the host PCB if the package were mounted on the top side. This means that the BGA’s balls are on the bottom layer of the cross-section. Your dies are mounted on the top. For wire ...

Sharp angles, whether they create a spike in a poured shape or form an acid trap between two different pieces of metal, are a problem for us all. And as designers, we will go out of our way to try and avoid creating these situations; they will still ...

If you ever have the need to remove an area of your design, you may find it to be a more complex process than you would think. Shapes in that area will, if you select them with show element, want to pick up the entire shape. That may extend well outs...

I think every traditional package designer understands what a plating bar is and the purpose it serves. There to provide electric current during the manufacturing process, each net is connected out to the perimeter of the BGA, which allows for the cu...

Having coincident edges shared across multiple layers is frequently not a desirable situation to be in. Just as we don’t appreciate degassing holes at the same position on adjacent layers – which can lead to dips or valleys in the finishe...

As the component count increases in package/interposer designs, many more of you are turning to front-end schematic tools for managing the netlist and connectivity. When working directly inside the layout design, however, there remain many cases wher...

If you are using Allegro Package Designer Plus with the Silicon Layout option to design your substrates, it is likely that you are also using a formal verification platform such as Cadence Pegasus or PVS to check your physical layout against the logi...

Degassing, other times called outgassing, is a common operation in IC package and interposer designs. As the name implies, the technology allows for gases to escape during the manufacturing process and prevent bubbling. It has a second benefit &ndash...

We talked a few months ago regarding why flip-chip padstacks are single layer pads in your design. Today, I wanted to spend just a few minutes looking at a variation on this issue that has come across my inbox more than once since that post went up. ...

Last week we introduced you to the new dark theme. But, we listen to your suggestions for ideas of other ways to improve your ability to move around your design efficiently. That brings me to two other items which you have your peers in our loyal com...