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  • Tyler
    IC Packagers: A New Way to Create Structures
    By Tyler | 9 Feb 2021
    Let’s focus today on an established routing technology with a new twist! All of you are doubtless familiar with the concept of structures – formerly called via structures, renamed to structures because of their growing flexibility and application across many flows.
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    IC Packaging and SiP Design | 17.4 | Allegro Package Designer | 17.4-2019
  • Tyler
    IC Packagers: An Introduction to Off-Grid Degassing
    By Tyler | 2 Feb 2021
    All of you doing advanced node package or silicon interposer substrate design in Allegro® Package Designer know what degassing is. And, while we talked last summer about massive performance improvements (plus additional information in show elemen...
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    IC Packaging and SiP Design | 17.4 | Allegro Package Designer | 17.4-2019
  • Tyler
    IC Packagers: A Final Set of Reasons to Move to 17.4 HotFix 013
    By Tyler | 26 Jan 2021
    I could doubtless extend this series all year long, covering the important updates, improvements, and completely new functionality that is continually being added to the Allegro® Package Designer product. This will be my last before we shift back...
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    IC Packaging and SiP | 17.4 QIR2 | Allegro Package Designer | 17.4-2019
  • Tyler
    IC Packagers: More Reasons to Move to 17.4 HotFix 013
    By Tyler | 19 Jan 2021
    As promised, we’re back with some more of the big improvements that are part of the QIR2 update release of 17.4 (HotFix 013). This time, everything is specific to our Allegro® Package Designer Plus community. Without further ado, then, let&...
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    IC Packaging and SiP Design | 17.4 | Allegro Package Designer | 17.4-2019
  • Tyler
    IC Packagers: Exciting New Updates and Reasons to Move to 17.4 Hotfix 013
    By Tyler | 12 Jan 2021
    Welcome to a brand-new year, everyone! As we welcome in 2021, we also welcome the next major update to the 17.4 Allegro platform release in the form of QIR2 (hotfix 13). These new updates are exciting for many reasons. Of course, they bring bug fixes...
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    IC Packaging and SiP Design | 17.4 | Allegro Package Designer | 17.4-2019
  • Auromala
    The Year That Was: Cadence IC Packaging and SiP Blogs in 2020
    By Auromala | 24 Dec 2020
    And so, here we are at the end of the year. I do hope that our weekly IC posts livened up 2020's groundhog days full of online meetings, washing up, and frantic searches for an Icelandic crime series you haven't yet watched! As we take stock ...
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    Cadence Design Systems | 17.4 | SiP | IC Packaging | IC Packaging & SiP design | Allegro Package Designer | 17.4-2019
  • Tyler
    IC Packagers: Copying Objects across Layers and Classes
    By Tyler | 22 Dec 2020
    Some items are useless on multiple levels. The most common multi-class pairing is probably the package substrate outline and the route/component keep-in shapes. Since it’s unwise to route or place anything off the edge of the world, it is impor...
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    IC Packaging and SiP Design | 17.4 | Allegro Package Designer | 17.4-2019
  • Tyler
    IC Packagers: Comparing Design Versions to Find Physical Changes
    By Tyler | 15 Dec 2020
    ECOs. Without them, the lives of designers would be so much easier! Imagine a world where the original requirements you were given never changed throughout the design. Unfortunately, such a world, as we know, does not exist. How, then, can you track ...
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    IC Packaging and SiP Design | 17.4 | Allegro Package Designer | 17.4-2019
  • Tyler
    IC Packagers: Leaving Yourself Reminders in Your Designs
    By Tyler | 8 Dec 2020
    Are you like me? Do you forget things and have a running to-do list for your designs? Would you like to leave instructions and comments for your colleagues to remind them of actions needing doing? There are many places to record this type of informat...
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    17.4 | IC Packaging & SiP design | Allegro Package Designer | 17.4-2019
  • Tyler
    IC Packagers: Adding Multiple Component Instances without a Schematic
    By Tyler | 1 Dec 2020
    More package designers these days, with the increasing component counts and more complicated electrical constraints, are shifting to using a front-end schematic capture tool. As with IC and PCB design, this allows for verification between the logical...
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    IC Packaging and SiP Design | Allegro Package Designer | 17.4-2019
  • Tyler
    IC Packagers: How to Define Your Own Team-Certified Wire Profiles
    By Tyler | 23 Nov 2020
    Back at the start of 2020, we talked about why you shouldn't use the default wire profile in your actual design. Today, I want to take this a step further. If you do wire bond designs, you are doubtless aware of the certified bond wire profiles t...
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    IC Packaging & SiP design | Allegro Package Designer | 17.4-2019
  • Tyler
    IC Packagers: Why You Can’t Start a Co-Design Die in Allegro Package Designer
    By Tyler | 17 Nov 2020
    Let’s investigate this question today, as I’ve been asked a few times over the years by curious designers. The question is one of wanting to start from the Allegro Package Designer environment and begin prototyping a die pin layout. If yo...
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    IC Packaging & SiP design | Allegro Package Designer | 17.4-2019
  • Tyler
    IC Packagers: Key Functions for Good SKILL Programming in Allegro Package Designer
    By Tyler | 10 Nov 2020
    Many of you out there are SKILL coders (or have these people on your team). SKILL is the extension programming language for all the backend layout products in the Allegro family, including Allegro Package Designer. If you’ve read up on the blog...
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    17.4 | IC Packaging & SiP design | Allegro Package Designer | 17.4-2019
  • Tyler
    IC Packagers: Allegro Package Designer and 3D DXF
    By Tyler | 3 Nov 2020
    Hello, all. As we push towards the next major update to the 17.4 release, the team here at Cadence is very busy! We hope you’ll be as excited by the new updates, enhancements, and bug fixes as we are. But until then, there is still plenty of ca...
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    IC Packaging & SiP design | Allegro Package Designer | 17.4-2019
  • Tyler
    IC Packagers: Controlling Voids around Critical Signals
    By Tyler | 27 Oct 2020
    With greater and greater counts of high-speed and differential pair signals in designs, the ability to control the areas around these nets becomes more important. Adjusting and maintaining the distance to these nets on the same layer as the routing i...
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    IC Packaging and SiP | Allegro Package Designer | 17.4-2019
  • Tyler
    IC Packagers: Extending Pins with Structures
    By Tyler | 20 Oct 2020
    When you are placing components (or defining your BGA pattern), often it is necessary to escape each of those pins to a given internal layer. This could be to get your power and ground supply to the designated plane layer. Or, it might be the first s...
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    IC Packaging & SiP design | Allegro Package Designer | 17.4-2019
  • Tyler
    IC Packagers: Accurate Masking of Your Substrate Layers
    By Tyler | 13 Oct 2020
    Soldermask and its brethren are stable in the EDA design industry. These layers control what is exposed to the elements (and to electrical connections!) on the top and bottom layers of the substrate. But, for many years, they have been a part of the ...
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    IC Packaging & SiP design | Allegro Package Designer | 17.4-2019
  • Tyler
    IC Packagers: Battening the Hatches After Going to Manufacturing
    By Tyler | 6 Oct 2020
    When you send the initial version of your design for manufacturing, it’s a huge sense of accomplishment. Things are complete. All constraints have been met. When the part comes off the manufacturing line, it works. That is something to be proud...
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    IC Packaging & SiP design | Allegro Package Designer | 17.4-2019
  • Tyler
    IC Packagers: The Importance of Proper DC Net Identification
    By Tyler | 29 Sep 2020
    It may surprise some of you, but I often receive databases in which the power and ground nets are not properly identified. Many times, I get these with questions about slow performance during editing actions in the design or a basic confusion of why ...
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    IC Packaging and SiP | Allegro Package Designer | 17.4-2019
  • Tyler
    IC Packagers: Creating Standards-Compliant Packages
    By Tyler | 22 Sep 2020
    When you are creating a BGA package component, you are, almost certainly, going to be implementing one that adheres to JEDEC standards. This means selecting from a set of available package size and pin pitch combinations, using a specific, grid-based...
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    IC Packaging | Allegro Package Designer | 17.4-2019
  • Tyler
    IC Packagers: Shrinking Dies Inside the Package Layout
    By Tyler | 15 Sep 2020
    There are many reasons a die’s size in the package doesn’t match the design size recorded in the IC layout tool. For starters, the IC layout doesn’t always include the scribe lines and other manufacturing offsets/adjustments that do...
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    IC Packaging | Allegro Package Designer | 17.4-2019
  • Tyler
    IC Packagers: Preparing a Completed Package for Mounting on a PCB
    By Tyler | 8 Sep 2020
    We’ve covered all the different types of die components and how they interface with the package substrate coming into Allegro Package Designer. But, the package component (whether it’s a BGA, LGA, lead frame, or something else) is destine...
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    IC Packaging and SiP | Allegro Package Designer | 17.4-2019
  • Tyler
    IC Packagers: How Die Stacking Works in Allegro Package Designer
    By Tyler | 1 Sep 2020
    Recently, we’ve covered some basics about why imported dies default to chip-down flip-chips and even the different types of mirroring . To close on the topic of dies, die stacks, and the interaction of components why may interface together witho...
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    IC Packaging | Allegro Package Designer | 17.4-2019
  • Tyler
    IC Packagers: Establishing Connectivity Between Die and BGA
    By Tyler | 25 Aug 2020
    The BGA component serves the primary role of redistributing the signals from the die it protects to an interface pattern (the BGA’s balls) compatible with the host PCB it mounts on. As a result, many IC package designs are among those who do no...
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    17.4 | IC Packaging | Allegro Package Designer | 17.4-2019
  • Tyler
    IC Packagers: Designing a Package from the Flip-Chip’s Perspective
    By Tyler | 18 Aug 2020
    Most package substrates are designed as they will be placed onto the host PCB if the package were mounted on the top side. This means that the BGA’s balls are on the bottom layer of the cross-section. Your dies are mounted on the top. For wire ...
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