Cadence Community

IC Packagers: Accelerate Complex Degassing with 17.4

By Tyler | 30 Jun 2020

Degassing, other times called outgassing, is a common operation in IC package and interposer designs. As the name implies, the technology allows for gases to escape during the manufacturing process and prevent bubbling. It has a second benefit &ndash...

0 Comments

Tags:

IC Packaging | Allegro Package Designer
IC Packagers: How to Fix Padstacks that Aren’t Showing All Their Layers

By Tyler | 24 Jun 2020

We talked a few months ago regarding why flip-chip padstacks are single layer pads in your design. Today, I wanted to spend just a few minutes looking at a variation on this issue that has come across my inbox more than once since that post went up. ...

0 Comments

Tags:

Allegro Package Designer
IC Packagers: Navigating Your Visible Design

By Tyler | 16 Jun 2020

Last week we introduced you to the new dark theme. But, we listen to your suggestions for ideas of other ways to improve your ability to move around your design efficiently. That brings me to two other items which you have your peers in our loyal com...

0 Comments

Tags:

17.4 | Allegro Package Designer | Allegro PCB Editor
IC Packagers: Welcome to the Dark Side

By Tyler | 10 Jun 2020

The 7th ISR (HotFix 007 or QIR1) for the 17.4 release is available for download now. This marks the first major update for the 17.4 software stream, and what an update it is! You’ll notice many new things when you download and install the new build. Let’s tal...

0 Comments

Tags:

Allegro Package Designer | Allegro PCB Editor
IC Packagers: Count Your Fingers (Without Using Your Toes)

By Tyler | 3 Jun 2020

Let’s talk about wire bonding today! More specifically, the unique labels assigned to every bond finger in your design and how these are import for documentation and your bonding engineer. Bond finger labels are like physical pin numbers on you...

0 Comments

Tags:

Allegro Package Designer
IC Packagers: Keep Fan-Out Routing Aligned During ECOs

By Tyler | 26 May 2020

When a change comes in from your IC design partner, it can be met with trepidation. How drastic is the change? What impact will it have on the package routing and (potentially) even the layer count needed to fan out the die? Will the bond finger tier...

0 Comments

Tags:

Allegro Package Designer
IC Packagers: Determining Minimum Spacing Values in a Design

By Tyler | 19 May 2020

I don’t remember the first time I was asked this question. At its core, the question was one of finding not the minimum constraint value in the design, but instead the minimum ACTUAL spacing value for a given set of objects in the design. As we...

0 Comments

Tags:

Allegro Package Designer
IC Packagers: The Choice Between Static and Dynamic Shapes

By Tyler | 12 May 2020

That title might be a touch misleading. We’re not here to talk about why to convert shapes between static and dynamic. Rather, I want to talk about why you should NOT be doing this. Every design has some conductor shapes in it (or at least a ve...

0 Comments

Tags:

Allegro Package Designer | Allegro PCB Editor
IC Packagers: Advanced In-Design Symbol Editing

By Tyler | 6 May 2020

We have talked about aspects of the in-design symbol edit application mode in the past. This is the environment specific to the Allegro Package Designer layout tools allowing you to work on symbol definitions directly in the context of your layout de...

0 Comments

Tags:

Allegro Package Designer
IC Packagers: Shape Connectivity in the Allegro Data Model

By Tyler | 28 Apr 2020

Those who work in the IC Packaging design space have some unique challenges. We bridge between the IC design world (90/45-degree traces with rectangular and octagonal pins) and the PCB domain (any-angle routing, filled planes, and a multitude of pad ...

0 Comments

Tags:

Allegro Package Designer | Allegro PCB Editor
IC Packagers: You Can Leave Your (Molding) Cap On…

By Tyler | 21 Apr 2020

Molding caps aren’t something we talk about too frequently around here. We all know they exist, and they serve an important purpose of protecting the delicate die from potentially harsh environmental conditions. They impact how well heat can be...

0 Comments

Tags:

Allegro Package Designer
IC Packagers: Time-Saving Alternatives to Show Element

By Tyler | 14 Apr 2020

In the Allegro back-end layout products like Allegro Package Designer Plus, it would be reasonable to assume that the most often used command is none other than “show element” (shortcut key F4). This command, runnable at nearly any t...

0 Comments

Tags:

Allegro Package Designer | Allegro PCB Editor
IC Packagers: A New Option in Bond Finger Solder Mask Openings

By Tyler | 7 Apr 2020

If you design wire bond packages, you’re familiar with the need for the bond fingers and rings on the package substrate layers to be exposed through the solder mask layer. If they aren’t, it becomes… rather difficult… to bon...

0 Comments

Tags:

Allegro Package Designer
IC Packagers: Don’t Get Stranded on Islands, Delete Them!

By Tyler | 31 Mar 2020

No, this isn’t a Hollywood movie. We’re talking about pieces of plane shapes with no connections to them, not an idyllic private oasis in the Caribbean (sorry). Removing shape islands is something you’ve always been able to do in th...

0 Comments

Tags:

Allegro Package Designer | Allegro PCB Editor
IC Packagers: Identify Your Components

By Tyler | 24 Mar 2020

We’ve all seen bar codes and the more modern QR codes. They’re everywhere you go – items at the grocery store, advertisements and posters, even on websites. Did you know that, with the productivity toolbox in Allegro Package Designe...

0 Comments

Tags:

Allegro Package Designer | Allegro PCB Editor
IC Packagers: Design Element Label Management

By Tyler | 18 Mar 2020

A few weeks ago, we talked about template text labels for design-specific information. There, we were focused on labels that are specific to the design as a whole: revision information, dates, authors, etc. Today, we’re looking at a diff...

0 Comments

Tags:

Allegro Package Designer | Allegro PCB Editor
IC Packagers: The Different Types of Mirrors

By Tyler | 10 Mar 2020

I’m not talking about carnival funhouse mirrors, but rather the different options for mirroring symbols, vias, and bond fingers in your IC Package layout. The Allegro Package Designer Plus and SiP Layout tools have two distinct styles of m...

0 Comments

Tags:

Allegro Package Designer
IC Packagers: Five Steps to IC-Driven Package Design

By mrigashira | 5 Mar 2020

They say Moore's law is slowing. It may be slowing but it is still running - it has not stopped! And, it has been running at full throttle for quite a few decades now. The net result of this run? Well, you can't design ICs in isolation from the...

0 Comments

Tags:

Allegro Package Designer
IC Packagers: Variable Text Labels and Template Reuse

By Tyler | 25 Feb 2020

For many, the information labels always go in a consistent location in the design so that they appear at the same location on a printout of the design. If you want these text elements in the same place in all your designs, but each design has its own set of values ...

0 Comments

Tags:

Allegro Package Designer | Allegro PCB Editor
IC Packagers: An Introduction to Via Arrays

By Tyler | 18 Feb 2020

Vias are present in every design (except maybe some lead frames and the very rare single-layer substrate). Where they are placed, and how many there are, will depend on a slew of factors, though, as we know. There are different situations and reasons...

0 Comments

Tags:

Allegro Package Designer
IC Packagers: RF Symbols, Coils, and Structures in IC Packages

By Tyler | 11 Feb 2020

So, you need to add more complicated structures into your package design. What options do you have available to you in the Cadence packaging products with the 17.4 release – whether you’re using the base Allegro Package Designer Plus or h...

0 Comments

Tags:

Allegro Package Designer
IC Packagers: A Boundless Bounty of Bounding Shapes

By Tyler | 4 Feb 2020

How’s that for a tongue twister? Go ahead, try and say it three times fast! What we’re talking about today is the “Create Bounding Shapes” tool found in the Shapes menu of both Allegro Package Designer and SiP Layout. We first...

0 Comments

Tags:

Allegro Package Designer
IC Packagers: Mysteries Revealed - Why Is Flip-Chip Chip-Down the Default Library Die Orientation?

By Tyler | 28 Jan 2020

We’ve come to the end of my New Year’s Resolutions for 2020. Before we dive deeper into the exciting new capabilities to be found in the 17.4 release, though, I’d like to address a question I hear from new users all the time. That q...

0 Comments

Tags:

Allegro Package Designer
IC Packagers: Symbol Editing in IC Packages - Choose the Right Option

By Tyler | 21 Jan 2020

When you need to make an edit to a component, whether that is the BGA footprint in need of a pin #1 padstack change for reference of adjustments to the entire bump layout of a flip-chip to feed routability changes back to the IC design team, there ar...

0 Comments

Tags:

Allegro Package Designer
IC Packagers: The Default Bond Wire Profile - PROFILE1 (And Three Reasons Why Not to Use It)

By Tyler | 14 Jan 2020

For those of you who do wire-bond package substrate – whether you’re designing a single-chip leadframe, a multi-die memory stack, or a complex stack with wire-bonds, flip-chips, interposers, and spacers all in one – you need wire pr...

0 Comments

Tags:

Allegro Package Designer

IC Packaging and SiP Blogs