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IC Packagers: Choosing the Right Netlist to Match Your Needs

By Tyler | 20 Aug 2019

Netlists. Everyone needs them! But what you are using your netlist for can have a significant influence on just what KIND of netlist you want. Fortunately, the Cadence SiP tools offer formats for just about every situation you might run into, from in...

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APD | IC Packaging & SiP design | SiP Layout
IC Packagers: Grouping Items with Symbol Instances

By Tyler | 13 Aug 2019

Whether you’re adding lines, text, shapes, routing elements, or any other feature to the design, most elements assume that you are placing them at the design level. If they are part of the symbol, they would be part of the library object. Is there a quick and convenient way to take the additional elements and assign them to the placed symbols in your design so that everything stays together in easy to manipulate pieces...

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IC Packaging | SiP Layout
IC Packagers: Six Steps of IC Packaging

By mrigashira | 6 Aug 2019

Do you want to create an IC Package and are on the lookout for a tool that suits you? Or, you might already be using APD or SiP Layout but want to know their full potential. We will talk about six broad steps of IC Packaging and how APD and SiP Layout make the steps efficient and easy for you.

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APD | IC Packaging & SiP design | SiP Layout
IC Packagers: Multi-Wire Bonding with Ease Using Cadence IC Packaging Tools

By Tyler | 31 Jul 2019

When wire bonding, the most common situation remains a single wire from pin to finger. There may be die to die connections as you step down from one die to the next in a stacked die situation (sometimes called a stitch bond, where the wire is tacked ...

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APD | wirebonds | SiP Layout
IC Packagers: Correcting Die Orientations and Die Attachments

By Tyler | 23 Jul 2019

When you add a die component to your SiP Layout design, you must identify both its default attachment type – wire bond or flip-chip – and its orientation – chip up or down. But, what happens if you get this wrong? The most common re...

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APD | SiP Layout
IC Packagers: Bend in Both Directions with J-Loop Bond Wires

By Tyler | 16 Jul 2019

Let’s talk about wire bonding for a quick minute. Still a favorite for many of you, bonding is a cheap way to connect your die to the top layer of your package (or to a lead frame, if that’s what you’re using). A 3D wire is connecte...

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IC Packaging | APD | SiP Layout
IC Packagers: Balance Your Designs with Cadence SiP Layout

By Tyler | 9 Jul 2019

As designs get more complicated, package substrates are seeing more silicon-driven rules and structures. Substrate styles like fan-out wafer level packaging (FOWLP) and elements such as through-silicon vias (TSVs) being injected into the package lay...

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IC Packaging | APD | SiP Layout
IC Packagers: Vary Your Assembled Packages, Not Your Databases

By Tyler | 3 Jul 2019

Design variants are a common phenomenon, whether you design package substrates or PCBs. You may source a resistor from multiple vendors, and part of the design flow includes generating a bill of materials (BoM) which lists all the parts that go on a ...

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IC Packaging | APD | SiP Layout
IC Packagers: The Spaces Between Your Dies

By Tyler | 25 Jun 2019

Die stacks are starting to look more like skyscrapers every year. If your packages involved vertical stacks of components of any kind, then you know there is more involved in stacking your dies than just the components themselves. What about interpos...

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IC Packaging | APD | SiP Layout
IC Packagers: Constructing Components from Manufacturing Data

By Tyler | 20 Jun 2019

We’ve all been there. The only (or most accurate) data that we have for a component is the manufacturing data from another process. It could be a GDSII file for the top-layer metal of an IC or a Gerber film for the BGA ball pattern. If all you ...

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IC Packaging and SiP | APD | SiP Layout
IC Packagers: A Classic Revisited - Ball Map Spreadsheets

By Tyler | 11 Jun 2019

Interfaces to the major spreadsheet commands from OpenOffice, Microsoft, Google, and others are becoming more common in EDA, Cadence® SiP has had a great interface since early in the 16.6 release. You, our users, continue to find creative new use...

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APD | SiP Layout
IC Packagers: The (Copper) Pillars of Modern Design

By Tyler | 4 Jun 2019

Wire bonding has been around forever. Flip-chip mounting? That’s been around for a long time as well. Every new generation of packages brings with it new technologies, challenges, and options. Copper pillars have been around for a fair time as ...

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IC Packaging | IC Packaging and SiP | SiP Layout
IC Packagers: Dealing with Large Forms in Low Resolution Screens

By Monika | 3 Jun 2019

Our packages and boards are becoming complex and so are the design tasks we perform and the tools that we use. Although ease of use is the mantra for all our UIs, sometimes a form ends up having too many elements to address the ever-increasing requir...

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IC Packaging and SiP | Allegro Package Designer
IC Packagers: When Being Two-Sided is a Good Thing

By Tyler | 28 May 2019

With each new generation, demand for smaller, faster, lighter, more efficient is at the top of the requirements list for most things. But, we cannot make things smaller forever. Instead, we need to look for more creative solutions. Where can we ...

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IC Packaging & SiP design | SiP Layout
IC Packagers: Expanding Your (Thermal) Repertoire

By Tyler | 21 May 2019

The process of attaching a component to your package substrate involves many factors, including heat. What happens whenever heat is applied to something? Expansion, of course! How much your die expands during the assembly process will be influenced b...

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APD | CTE | Allegro Package Designer | SiP Layout
IC Packagers: Create Daisy Chain Substrates in a Flash with Cadence SiP Layout

By Tyler | 16 May 2019

How do you go about testing your IC or package substrate when it comes to physical endurance? For many of us, a daisy chain test package is a common option. With practical uses including extreme environmental and temperature testing scenarios, a dais...

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IC Packagers: Coming Soon to a Blog Near You…

By Tyler | 2 May 2019

What is new in the Cadence® SiP Layout and APD tools? Is there reason to get excited to pick up the most recent HotFix of 17.2 (or update from release 16.6 to 17.2 at all)? The answer is a most emphatic YES. Join us as we start our jo...

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Digital SiP design | IC Packaging & SiP design | Allegro Package Designer | SiP Layout
Take a lesson from the Amish...

By BillAcito | 19 Feb 2019

“Time to design completion” is almost always the primary metric and the cause for the most angst within a design team. Your customers demand that a package design is completed as quickly as possible to minimize the impact to the...

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collaboration | SiP | packaging | Symphony | IC package design
DesignCon 2019: Is this the Year?

By BillAcito | 15 Jan 2019

2019 has started --- is this the year of advanced packaging, where system design enablement shifts to the package? If you are attending DesignCon (designcon.com) in Santa Clara, California, in a few weeks, there’s a robust agenda, and it might ...

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DesignCon | packaging
How Can I Assess Process Variation in My IC Package Design?

By BillAcito | 20 Nov 2017

In a previous blog we talked about the IC Packaging Design Variant tool. As you recall, this tool extended and eased the practice of a designer creating one database that represented multiple configurations of the same general design. Rather than man...

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SiP | design variants | IC package design | APD | manufacturing | 17.2
Reports – Now Sorting Your Strings the Way YOU Want Them Sorted

By ICPackagingPro | 25 Mar 2016

When it comes right down to it, if we asked most of you what was the most important feature to you, many would probably answer with things like routing, wire bonding, net assignment optimization, or DRC checks. All great responses, and each of them a...

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documentation | Cadence Design Systems | Reports | manufacturing exports | APD | Allegro Package Designer | IC packaging documentation | SiP Layout | sorting
Designing a New Component from Scratch Inside Your Layout Environment

By ICPackagingPro | 11 Mar 2016

Have you ever needed to build a component with a custom, complex pin pattern? Have you ever wanted to do so within the context of the substrate you’re working on (or, for that matter, needed to build a custom package based on a set of dies you need packaged...

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IC package design | APD | package design | Allegro Package Designer | SiP Layout | substrate design tools
How to Overlay Shapes on Top of Sets of Reference Objects with the Latest Cadence IC Packaging Tools

By ICPackagingPro | 22 Feb 2016

Many of you are familiar with the bond finger soldermask opening creation tool—used for years, it allows you to create a single, smooth hole in your soldermask shapes that exposes all the bond fingers in a single row of fingers. Rather than having indents...

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bounding shapes | SiP | IC package design | APD | beta tools | package design | shapes
How to Maximize Performance When Your Package Layout Gets Complicated

By ICPackagingPro | 5 Feb 2016

We are all familiar with it. Every year, designs get faster, smaller, and more complicated. Whether your newest package has a towering stack of memory dies placed into a cavity or a few massive flip-chips with critical bus lanes between them, it never...

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Cadence Design Systems | SiP | Digital SiP design | IC package design | APD | package design | Allegro Package Designer
Customize the Organization of Bond Wires in Your Artwork Films with SiP Layout and Allegro Package Designer

By ICPackagingPro | 15 Jan 2016

When it comes to IC Package substrates, Gerber is still one of the most common, most popular formats used to send the design for manufacturing. Being a strictly 2D format, however, how do you best fit bond wires into your artwork films if you want to...

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SiP | Allegro package design | Digital SiP design | IC package design | APD | package design | manufacturing | wirebonding | substrate design tools

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