• Discussion

  autorouting on a layer with a copper shape Locked

  12874 views
  1 reply
  Latest over 15 years ago
  by redwire
• Discussion

  problem with mmsim61 Locked

  16061 views
  6 replies
  Latest over 15 years ago
  by Tawna
• Discussion

  How target nets in a relative delay group are determined in the specctra autorouter? Locked

  14862 views
  1 reply
  Latest over 15 years ago
  by tomoo
• Discussion

  silkscreen ref des text - how does one edit it and add it in layout? using 16.2 Locked

  3376 views
  3 replies
  Latest over 15 years ago
  by K2J4
• Discussion

  IP genericity Locked

  13163 views
  0 replies
  Started over 15 years ago
  by maroua
• Discussion

  canit able to connect the ports Locked

  13696 views
  1 reply
  Latest over 15 years ago
  by StephenH
• Discussion

  No Thermal Pad - Negative shape? Locked

  1245 views
  2 replies
  Latest over 15 years ago
  by Pedrator
• Discussion

  Schematic entry parameter as a function of instance name Locked

  16474 views
  7 replies
  Latest over 15 years ago
  by yoyega
• Discussion

  Where to setup shape path in Pad Designer Locked

  14853 views
  2 replies
  Latest over 15 years ago
  by MartinDude
• Discussion

  function call

  13384 views
  2 replies
  Latest over 15 years ago
  by tltoth
• Discussion

  CIW > File > Import > Verilog... fails to create schematics (portOrder property?) Locked

  2801 views
  1 reply
  Latest over 15 years ago
  by Quek
• Discussion

  hiCreateReportField() warnings Locked

  14335 views
  1 reply
  Latest over 15 years ago
  by Andrew Beckett
• Discussion

  removing backslashes

  16826 views
  7 replies
  Latest over 15 years ago
  by Ejlersen
• Discussion

  Allegro Design CIS pin naming Locked

  13522 views
  2 replies
  Latest over 15 years ago
  by Mstrghettorigg
• Discussion

  If statements in env file? Locked

  16608 views
  3 replies
  Latest over 15 years ago
  by fxffxf