Problem with MOS Bulk Routing Parasitic Resistance Extraction

This is to be expected unless you do substrate extraction. The substrate will be treated as a single net, and so all bulk connections will be ideal. There is the option in QRC to do substrate extraction too, but this can generate a very large mesh of resistors so be warned - most of the time it is not necessary unless you really are trying to investigate some detailed coupling through the substrate.

Regards,

Andrew.

Thanks Andrew,

Our design kits do not provide the substrate model. Only the substrate resistivity and thickness are known. Is there any way to create a simple model for the QRC extractor based on these two parameters?

If not, can I disable the bulk "shortcircuit" to the global polarization nets and at least count with the bulk contact and metal (not substrate) routing parasitic resistances?

Being suspicious of them, I ran simulations using boldly modified netlist incorporating some of these resistances manually. The results coincide approximately with the experimental data according to which my 18-bit ADC looses 2 bits of resolution. Nevertheless, I still need more accurate netlist for more realistic simulations.

Thank you,

Stepan.

Hi Stepan

The difficulty is, the bulk is under the transistor - and how do you know which substrate tap is the one that is connecting to it? One approach might be to write rules in the LVS to create pseudo islands or wells under the transistors - these don't exist in reality, but you could effectively try to treat each of these regions as unconnected from each other, and only connected via the substrate taps. Of course, you'd need to ensure that these substrate regions are big enough to include a substrate tap near the transistor.

Then the behaviour would be similar to your n-wells (if a p-substate process) or vice-versa.

All this would involve changing the LVS extraction rule deck. 

There's not (as far as I know) any magic switch to do this isolation of the bulks automatically (at least not making sure they are connected up to a suitable tap).

Regards,

Andrew.

Thanks Andrew,

Following your opinion, I delved into LVS extraction rule scripts.

The PMOS transistor is extracted such:

extractMOS( "P_18_MM" pgate_mm ply("G") psd("S" "D") wel("B") flagMalformed )

where wel is previously declared as:

wel= geomAndNot( nwell welres )

being nwell:

nwell = geomAndNot( NWEL TWEL )

and NWEL:

NWEL = layer( "NWEL" type("drawing") )

A part, the connectivity section mandates:

geomStamp( wel ntap )

geomConnect(
.....
            via( nsdcon   M1  nsd ntap )

.....)

According to these lines, it seems there is a clear connection definition reduced to few connection layers. I tried the following experiment:

Two separated NWELLs connected by a resistive path of M1. Each of two NWELLs contains one PMOS transistor with all terminals shortcircuited to the well polarization bias. And I would expect to obtain two separated nodes between two different NWELLS connected through this resistive M1 path. However, after extraction, the bulk terminal of this transistors is shortcircuited. Curiously, it does not happen with the sources of the same transistors which are connected through the parasitic resistance of M1 path.

Is there anything to see with the ivpcell of the transistor? Can I act on it to solve the problem?

Thank you,

Stepan.

Hi Stepan,

I don't really have the bandwidth to do a detailed investigation of the problem and research an answer. I just gave a very quick (and untested) suggestion, which may have been wrong or need some further work. As such, it would be best to work through this with customer support, so you can get somebody who can dedicate sufficient time to this (as you hopefully know, I answer on this forum in the spare moments I have here and there, but my day job keeps me pretty busy - especially at the moment!)

Regards,

Andrew.

Hi Andrew,

Finally, we have started interacting with the customer support of our foundry. They have extracted our cell using the same design kit, LVS and QRC state configuration script, but different version of Assura QRC UI:

                      Our version = 11.1

Foundry support version = 13.2.0

As a result, all the PMOS transistors have been extracted correctly with their bulk connected to the local parasitic resistors of the polarization metal paths. Nevertheless, all the NMOS transistors have still their bulk connected to the global ground. We understand that it should be solved by our means by rewriting the extraction script.

By now, we try to achieve at least a correct extraction for the PMOS transistors.

Is there any changes from QRC 11.1 to 13.2.0 version that we can incorporate without updating our version?

If you do not have this information, where we could find it?

Thanks,

Stepan.

This is an impossible question to answer (at least not without the full picture including the data and all the rule files), and to be honest given that the right solution is to use the version that the foundry have qualified against, there is little point trying to adapt things to use a 4 year old version of the software. What is the objection to updating to the version the foundry supports and have qualified against?

EXT132 is available on

Regards,

Andrew.

Hi Robin,

If you're still seeing a problem with the latest version, could you log this with customer support? I'd deal with it myself but I'm going to be out of the office most of the week.

Regards,

Andrew.