Cgg using AC analysis

Dear Elhossiny,

Elhossiny said:

how to get Cgg using AC analysis

Is your AC analysis GUI oppoint set to select "raw" as shown in the GUI panel a the Cadence On-line Support portal at URL:

https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1O3w000009xz7xEAA&pageName=ArticleContent

If you are not running a DC operating point analysis with your AC analysis, and want to examine operating point parameters (no node voltages) oppoint must be selected as "raw".

 Did you try this?

Shawn

thx for replay ,,

I cant open the pervious link

I want to get Cgg vs VGS, but using ac analysis only.

I tried V = I/(jwC), so C = I/(2πfV ), and assume f=1hz, but dont give me right cgg, can u tell me how to apply this equation to draw C-V curve use AC analysis.

Dear Elhossiny,

> I cant open the pervious link

Please consider getting a Cadence support account Elhossiny as there is a wealth of information on the site that I think you will find helpful. The account will provide access to the link. I have attached the relevant GUI AC analysis panel as Figure 1.

> I want to get Cgg vs VGS, but using dc analysis only.

I am confused. Your initial post and question suggested to me that you were only running an AC analysis only and wanted to find Cgg from the analysis without running a DC analysis. Did I misunderstand?

> I tried V = I/(jwC), so C = I/(2πfV ), and
> assume f=1hz, but dont give me right cgg,
> can u tell me how to apply this equation
> to draw C-V curve use AC analysis.

If you are trying to determine the C-V curve, you need to have a test bench to do this. You can not expect a single AC analysis to provide the C-V curve. I have described such a test bench in the past in this forum numerous times to examine the C-V relationship of any arbitrary two terminal device.

Is this what you want to do?

Figure 1

but its not two terminal device,, its gate terminal only

Dear Elhossiny,

Elhossiny said:

but its not two terminal device,, its gate terminal only

However, the capacitance you are interested in, Cgg I assume, can only be defined with respect to two nodes. In other words, any capacitance is a result of charge that gets stored and hence must be relative to some other node. In your case, I am assuming that Cgg, from the definition provided by Silvaco is:

"...the total gate capacitance (cgg), the low terminal of the measurement is connected to the drain, source and body nodes of the mosfet "

Hence, your "second" terminal is the common terminal formed by the source, drain, and bulk nodes of the MOS device.

Therefore, you must use a two terminal measurement to determine Cgg.

As an example of a means to estimate the capacitance versus voltage characteristic (which is I assume what you want), you might consider the examples I've provided in the Cadence community posts at URL:

https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/45219/simulating-mos-varactor

and

https://community.cadence.com/cadence_technology_forums/f/rf-design/48359/test-bench-for-plotting-negative-capacitance-of-cross-coupled-pair

The latter is the most recent post (I think) for which I provided a similar answer to your question.

Shawn