Custom IC Design

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VerilogA code error:signal exceeds blowup limit

Category: Custom IC Design

By Sandeep4386

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updated over 7 years ago by Sandeep4386

6 replies • 10041 views
Discussion

Missing Instances - inductor (lsps_otc)

Category: Custom IC Design

By Min Zee

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updated over 7 years ago by Andrew Beckett

1 replies • 3941 views
Discussion

Generate layout.oa for an older version of a layout (sync managed) and store it in an un-managed folder.

Category: Custom IC Design

By chaitdwivedi

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updated over 7 years ago by chaitdwivedi

4 replies • 15815 views
Discussion

Avoid/Blacklist model instance from PDK

Category: Custom IC Design

By HoWei

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updated over 7 years ago by Andrew Beckett

7 replies • 4029 views
Discussion

spectre oceaneval function documentation

Category: Custom IC Design

By StevenMikes

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updated over 7 years ago by Andrew Beckett

5 replies • 15748 views
Discussion

Monte Carlo dist=unif option

Category: Custom IC Design

By Michael H

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updated over 7 years ago by Michael H

4 replies • 1769 views
Discussion

How to plot frequency characteristic of capacitance?

Category: Custom IC Design

By kwsgk

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updated over 7 years ago by kwsgk

6 replies • 21053 views
Discussion

noisetype_off re-ignored

Category: Custom IC Design

By itos

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updated over 7 years ago by itos

2 replies • 14295 views
Discussion

question about the cdf parameters of the switch instance in analoglib

Category: Custom IC Design

By mhkvy4

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updated over 7 years ago by Andrew Beckett

1 replies • 15526 views
Discussion

Accessing parameters in an SOA (asserts) file from the Virtuoso environment

Category: Custom IC Design

By FormerMember

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updated over 7 years ago by FormerMember

2 replies • 5312 views
Discussion

Manipulate and copy from parametric analysis plot

Category: Custom IC Design

By BaaB

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updated over 7 years ago by Dimitra Papazoglou

1 replies • 14204 views
Discussion

Load pull - Differential

Category: Custom IC Design

By LucaA

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updated over 7 years ago by Alex Tiler

2 replies • 4786 views
Discussion

layout XL extract cellviews in hierarchy?

Category: Custom IC Design

By yeh1

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started over 7 years ago

0 replies • 14274 views
Discussion

import spice net list created from calibre lvs tool

Category: Custom IC Design

By programzombie

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updated over 7 years ago by Andrew Beckett

1 replies • 15182 views
Discussion

detecting process corner from within verilogA model

Category: Custom IC Design

By SoniaMK

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updated over 7 years ago by Saloni Chhabra

20 replies • 26130 views

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