Custom IC Design

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Discussion

variable $freq in veriloga

Category: Custom IC Design

By RobinCommander

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updated over 7 years ago by Frank Wiedmann

6 replies • 18400 views
Discussion

saving results with same net names of two different cells

Category: Custom IC Design

By EngrZM

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updated over 7 years ago by Andrew Beckett

3 replies • 14326 views
Discussion

Number of accepted tran steps in spectre log

Category: Custom IC Design

By anoopvk

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updated over 7 years ago by Andrew Beckett

1 replies • 14599 views
Discussion

Modifying an extracted view for post layout simulation.

Category: Custom IC Design

By ghrshomali

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updated over 7 years ago by Bruce A

16 replies • 25384 views
Discussion

Dynamically Changing the pulse width - vpulse/vsource

Category: Custom IC Design

By vijaykpd

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updated over 7 years ago by vijaykpd

4 replies • 8762 views
Discussion

How to tell spectre (in ADE L) to enable "monte carlo" mode

Category: Custom IC Design

By itos

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updated over 7 years ago by Andrew Beckett

1 replies • 2748 views
Discussion

ADEXL: Making Dependent Tests

Category: Custom IC Design

By BrJaWr

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updated over 7 years ago by Andrew Beckett

8 replies • 24360 views
Discussion

Simulation with verilog-a model

Category: Custom IC Design

By HANNN

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updated over 7 years ago by Andrew Beckett

3 replies • 17564 views
Discussion

Assura DRC doesn't zoom to errors

Category: Custom IC Design

By spaceradlab

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updated over 7 years ago by Andrew Beckett

1 replies • 1267 views
Discussion

how to process parametric sweep result in adexl

Category: Custom IC Design

By sjwprc

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updated over 7 years ago by Andrew Beckett

1 replies • 16690 views
Discussion

Use via variant with auto via or via stack?

Category: Custom IC Design

By MatthewLove

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updated over 7 years ago by Marc Heise

1 replies • 14427 views
Discussion

VNCAP error

Category: Custom IC Design

By EngrZM

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updated over 7 years ago by Andrew Beckett

1 replies • 14103 views
Discussion

Nested Sweeps in ADE XL

Category: Custom IC Design

By MicheleA

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updated over 7 years ago by Andrew Beckett

5 replies • 17736 views
Discussion

LAYOUT XL - auto route - route with wire assistant overrides

Category: Custom IC Design

By anandmohan

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started over 7 years ago

0 replies • 2371 views
Discussion

Fail to run with user defined the "connect rules"

Category: Custom IC Design

By fatcat1206

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updated over 7 years ago by Andrew Beckett

6 replies • 6913 views

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