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Custom IC Design

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  • Discussion

    Pins are not annotated using subcircuit (netlist)

    Category: Custom IC Design

    By Johanny Saenz

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    updated over 8 years ago by Johanny Saenz

    4 replies • 15886 views
  • Discussion

    Measure DNL/INL in ADE-XL

    Category: Custom IC Design

    By migrg

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    updated over 8 years ago by migrg

    1 replies • 9071 views
  • Discussion

    dft error with a valid transient waveform

    Category: Custom IC Design

    By Aldo2

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    updated over 8 years ago by Aldo2

    4 replies • 15250 views
  • Discussion

    Problem in importing verilog netlist to cadence

    Category: Custom IC Design

    By Casp

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    •

    started over 8 years ago

    0 replies • 14054 views
  • Discussion

    Verilog-A, one time execution function

    Category: Custom IC Design

    By samer1

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    updated over 8 years ago by samer1

    6 replies • 21617 views
  • Discussion

    scs files

    Category: Custom IC Design

    By samer1

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    •

    updated over 8 years ago by Quek

    6 replies • 26799 views
  • Discussion

    Exporting ADE-L Variables

    Category: Custom IC Design

    By netbug

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    •

    updated over 8 years ago by netbug

    6 replies • 15277 views
  • Discussion

    unwanted snapping in layout editor

    Category: Custom IC Design

    By huadel

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    •

    updated over 8 years ago by Andrew Beckett

    1 replies • 16631 views
  • Discussion

    Using DC operating point calculated from spectre in APS Simualtion over Corners

    Category: Custom IC Design

    By Johanny Saenz

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    •

    started over 8 years ago

    0 replies • 13859 views
  • Discussion

    What is license feature "Virtuoso_Spectre_GXL_MMSIM_Lk", and how to use it?

    Category: Custom IC Design

    By dontpanic

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    •

    updated over 8 years ago by dontpanic

    2 replies • 4137 views
  • Discussion

    stb and tran analysis discrepancy

    Category: Custom IC Design

    By FormerMember

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    •

    updated over 8 years ago by FormerMember

    1 replies • 1532 views
  • Discussion

    [Solved] Unbound pins when running Assura LVS in Virtuoso Layout Suite L

    Category: Custom IC Design

    By dpalomeq

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    •

    updated over 8 years ago by dpalomeq

    8 replies • 22241 views
  • Discussion

    ADE: Use of nested design variables in output expressions

    Category: Custom IC Design

    By sommer

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    •

    updated over 8 years ago by Andrew Beckett

    3 replies • 17131 views
  • Discussion

    Access simulation data with OCEAN command getResult() / method description of classType famLeafAnalysis

    Category: Custom IC Design

    By sommer

    $usertype

    •

    started over 8 years ago

    0 replies • 13440 views
  • Discussion

    How to set different accuracy settings for different time periods in transient simulation.

    Category: Custom IC Design

    By vamshiky

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    •

    updated over 8 years ago by Andrew Beckett

    6 replies • 25068 views
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