Custom IC Design

Latest Posts

Discussion

VCO design problem

Category: Custom IC Design

By asrf

$usertype
•
updated over 5 years ago by FormerMember

9 replies • 24773 views
Discussion

ViVA XL export to vcsv failed

Category: Custom IC Design

By ZoltanT

$usertype
•
updated over 5 years ago by ZoltanT

4 replies • 16552 views
Discussion

PSS sweep in ADE-XL

Category: Custom IC Design

By ZoltanT

$usertype
•
updated over 5 years ago by ZoltanT

4 replies • 16761 views
Discussion

Parameters in hierarchical schematics

Category: Custom IC Design

By pepijndevos

$usertype
•
updated over 5 years ago by Andrew Beckett

3 replies • 18485 views
Discussion

Is it possible to pour a plane in Virtuoso?

Category: Custom IC Design

By CADcasualty

$usertype
•
updated over 5 years ago by CADcasualty

2 replies • 13930 views
Discussion

Importing HSPICE .sp file and .lib libraries into Cadence Virtuoso

Category: Custom IC Design

By cadencenewbie

$usertype
•
started over 5 years ago

0 replies • 15860 views
Discussion

smooth dft

Category: Custom IC Design

By threepwood06

$usertype
•
updated over 5 years ago by threepwood06

5 replies • 16398 views
Discussion

Unit of self_gain in BSIM4(V4.5)

Category: Custom IC Design

By wgtkan

$usertype
•
updated over 5 years ago by Andrew Beckett

8 replies • 3833 views
Discussion

Exporting Cell Count and Cell Layers to text file

Category: Custom IC Design

By FLNaviGator

$usertype
•
started over 5 years ago

0 replies • 13172 views
Discussion

liberate error messages doc.

Category: Custom IC Design

By chaujohnthan

$usertype
•
updated over 5 years ago by Andrew Beckett

1 replies • 14005 views
Discussion

Noise analysis on dynamic comparator

Category: Custom IC Design

By minci

$usertype
•
updated over 5 years ago by Andrew Beckett

15 replies • 30258 views
Discussion

Noise spectral density of an amplifier

Category: Custom IC Design

By subhajitdey20

$usertype
•
updated over 5 years ago by Andrew Beckett

3 replies • 15498 views
Discussion

fsdb file not refreshed during simulation

Category: Custom IC Design

By Karev11

$usertype
•
updated over 5 years ago by Andrew Beckett

2 replies • 17454 views
Discussion

ADE L plotting error: vector::_M_range_check

Category: Custom IC Design

By ZoltanT

$usertype
•
updated over 5 years ago by Andrew Beckett

1 replies • 1604 views
Discussion

Some DRC errors regarding SP and DP

Category: Custom IC Design

By annieglez92

$usertype
•
updated over 5 years ago by annieglez92

2 replies • 14876 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.