Custom IC Design

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Discussion

How to increase font size of plots axis labels & markers in Cadence virtuoso

Category: Custom IC Design

By venkmanbuster

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updated over 5 years ago by Andrew Beckett

1 replies • 5882 views
Discussion

plotting noise via Matlab

Category: Custom IC Design

By wgtkan

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updated over 5 years ago by wgtkan

3 replies • 15308 views
Discussion

noise/jitter transfer function along clock-driven inverter chain

Category: Custom IC Design

By nicodega

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updated over 5 years ago by Frank Wiedmann

13 replies • 19369 views
Discussion

Specifying Operating Region Expressions Using the Operating Region Assistant Pane in ADEXL

Category: Custom IC Design

By NorNand

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updated over 5 years ago by NorNand

1 replies • 15513 views
Discussion

pnoise jitter and pnoise time average discrepency: what is the problem?

Category: Custom IC Design

By skylink

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updated over 5 years ago by skylink

12 replies • 26009 views
Discussion

Call Python Function from Verilog A Device Model

Category: Custom IC Design

By cerealkiller

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updated over 5 years ago by Herge

1 replies • 15121 views
Discussion

phase noise/vin vs. frequency

Category: Custom IC Design

By skylink

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updated over 5 years ago by skylink

2 replies • 2064 views
Discussion

What is thermal noise called

Category: Custom IC Design

By wgtkan

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updated over 5 years ago by wgtkan

2 replies • 16635 views
Discussion

Reading from a file in Verilog-A

Category: Custom IC Design

By Manev

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updated over 5 years ago by Andrew Beckett

4 replies • 18106 views
Discussion

monte carlo simulation

Category: Custom IC Design

By Nathan Chen

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updated over 5 years ago by Frank Wiedmann

2 replies • 15280 views
Discussion

Question on ADE Assembler (maestro) corner setup

Category: Custom IC Design

By yizhu1

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updated over 5 years ago by yizhu1

4 replies • 16810 views
Discussion

Save VHDL variables of specific hierachy

Category: Custom IC Design

By michael10

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updated over 5 years ago by michael10

2 replies • 14670 views
Discussion

Libraries not imported in the Library manager

Category: Custom IC Design

By UUinfini

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updated over 5 years ago by UUinfini

8 replies • 19114 views
Discussion

Does MC mismatch simulation reflect best or arbitrary layout ?

Category: Custom IC Design

By HoWei

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updated over 5 years ago by HoWei

4 replies • 17587 views
Discussion

Stability check issue during phase starting with 0 degree

Category: Custom IC Design

By MIN KIM

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updated over 5 years ago by Frank Wiedmann

3 replies • 19364 views

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