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Custom IC Design

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  • Discussion

    NCSU cdk does not have assura drc,lvs rcx rules.....

    Category: Custom IC Design

    By guru1984

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    started over 9 years ago

    0 replies • 843 views
  • Discussion

    virtuoso Segmentation fault

    Category: Custom IC Design

    By likelike

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    updated over 9 years ago by SanjayNITT

    8 replies • 26212 views
  • Discussion

    Make a variable as input of another expression in MC simulation

    Category: Custom IC Design

    By Junyi

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    updated over 9 years ago by Andrew Beckett

    1 replies • 14130 views
  • Discussion

    how do I attach technology library with new virtuoso lib

    Category: Custom IC Design

    By skillvt

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    •

    updated over 9 years ago by Andrew Beckett

    3 replies • 32941 views
  • Discussion

    Annotating bussed terminal voltages with cdsTerm()

    Category: Custom IC Design

    By tderstep

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    •

    updated over 9 years ago by Michele Ancis

    10 replies • 20141 views
  • Discussion

    Transient simulation strobing issues with xps

    Category: Custom IC Design

    By rsashwinkumar

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    started over 9 years ago

    0 replies • 13929 views
  • Discussion

    Problem building a slotted metal pcell

    Category: Custom IC Design

    By archive

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    •

    updated over 9 years ago by Andrew Beckett

    7 replies • 16605 views
  • Discussion

    QRC Extraction

    Category: Custom IC Design

    By kaydense

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    updated over 9 years ago by Andrew Beckett

    3 replies • 15744 views
  • Discussion

    Monte Carlo in ADE XL error

    Category: Custom IC Design

    By syen

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    updated over 9 years ago by Bsaoni

    5 replies • 17054 views
  • Discussion

    Monte Carlo simulation issues

    Category: Custom IC Design

    By saikatc

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    updated over 9 years ago by saikatc

    2 replies • 14428 views
  • Discussion

    Is that necessary to choose "save all" when creating a "savestate file", and re-start the simulation from it.

    Category: Custom IC Design

    By fatcat1206

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    updated over 9 years ago by Andrew Beckett

    3 replies • 1219 views
  • Discussion

    Failed to build VDB. Cannot submit DRC Run

    Category: Custom IC Design

    By V4vlsi

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    •

    updated over 9 years ago by kapiljainwal

    4 replies • 23434 views
  • Discussion

    Schematic terminals location and position for automated routing.

    Category: Custom IC Design

    By KishanVNs

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    updated over 9 years ago by Andrew Beckett

    3 replies • 15400 views
  • Discussion

    Assura LVS QRC extraction of only metal structure

    Category: Custom IC Design

    By MartinK

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    •

    updated over 9 years ago by Andrew Beckett

    3 replies • 15173 views
  • Discussion

    Transient info-time values not matching with the the transient values

    Category: Custom IC Design

    By RFStuff

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    •

    updated over 9 years ago by Andrew Beckett

    1 replies • 13647 views
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