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Custom IC Design

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  • Discussion

    Assura LVS using: setenv OA_UNSUPPORTED_PLAT linux_rhel40_gcc44x

    Category: Custom IC Design

    By bartman

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    updated over 9 years ago by Quek

    10 replies • 17275 views
  • Discussion

    Array manipulation in calculator

    Category: Custom IC Design

    By manudupouy

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    updated over 9 years ago by manudupouy

    3 replies • 16766 views
  • Discussion

    A divide by zero exception in connect_lib

    Category: Custom IC Design

    By twen

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    updated over 9 years ago by Andrew Beckett

    1 replies • 14444 views
  • Discussion

    DRD compactor versus stdcells

    Category: Custom IC Design

    By danmc91

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    •

    started over 9 years ago

    0 replies • 13726 views
  • Discussion

    ELC : Simulation status : FAIL during db_spice

    Category: Custom IC Design

    By Hemal93

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    •

    updated over 9 years ago by Hemal93

    6 replies • 15594 views
  • Discussion

    How to flatten layout cells and preserve pin names when pin names from different cells are the same

    Category: Custom IC Design

    By twen

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    updated over 9 years ago by Andrew Beckett

    10 replies • 21154 views
  • Discussion

    Issues with pin connectivity in Layout

    Category: Custom IC Design

    By DavideP

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    updated over 9 years ago by DavideP

    2 replies • 26224 views
  • Discussion

    Error in Calibre LVS

    Category: Custom IC Design

    By srihari18

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    updated over 9 years ago by Andrew Beckett

    1 replies • 17694 views
  • Discussion

    Run multiple ADE of the same schematic at the same time.

    Category: Custom IC Design

    By BaaB

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    updated over 9 years ago by BaaB

    4 replies • 17492 views
  • Discussion

    ELC Error: Redefinition of the subckt

    Category: Custom IC Design

    By Hemal93

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    updated over 9 years ago by Hemal93

    2 replies • 15096 views
  • Discussion

    abstract generator: LEF does not contain ANTENNAGATEAREA

    Category: Custom IC Design

    By jsundermeyer

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    updated over 9 years ago by jsundermeyer

    2 replies • 16212 views
  • Discussion

    BUG: Drawing path in Virtuoso 6.1.6 only possible in routing layers

    Category: Custom IC Design

    By Sheppy

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    updated over 9 years ago by ColinSutlieff

    5 replies • 16177 views
  • Discussion

    Post Layout Simulation Error

    Category: Custom IC Design

    By sdineshkumar

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    •

    updated over 9 years ago by Andrew Beckett

    1 replies • 14717 views
  • Discussion

    How to save current through inherited connections in a cell with AMS

    Category: Custom IC Design

    By twen

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    updated over 9 years ago by twen

    2 replies • 15804 views
  • Discussion

    How to create dependent voltage source?

    Category: Custom IC Design

    By BaaB

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    •

    updated over 9 years ago by Andrew Beckett

    9 replies • 24803 views
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