Custom IC Design

Latest Posts

Discussion

How can you move/stretch schematic wires WITHOUT Virtuoso rerouting everything and making a mess?

Category: Custom IC Design

By CADcasualty
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updated over 4 years ago by mmsaad66

2 replies • 5072 views
Discussion

Transient stop time for specified number of clocks

Category: Custom IC Design

By Senan
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updated over 4 years ago by Andrew Beckett

7 replies • 13946 views
Discussion

How to flatten GDS by stream out or Command

Category: Custom IC Design

By MollyMeow
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updated over 4 years ago by MollyMeow

2 replies • 10702 views
Discussion

Environment variable questions

Category: Custom IC Design

By sjwprcker
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updated over 4 years ago by sjwprcker

2 replies • 10365 views
Discussion

Simulating with a Calibre Extracted Netlist with ADE Explorer

Category: Custom IC Design

By jshumble
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updated over 4 years ago by jshumble

3 replies • 12429 views
Discussion

pstb analysis shows different results at different iprobe position

Category: Custom IC Design

By Irenexox
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updated over 4 years ago by FormerMember

1 replies • 11955 views
Discussion

Sort function to sort the paths selected using the bbox or beginpt or end pt

Category: Custom IC Design

By kumargbn
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updated over 4 years ago by kumargbn

2 replies • 10646 views
Discussion

How to detect EOF with Verilog-ams fscanf?

Category: Custom IC Design

By Martinsh
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started over 4 years ago

0 replies • 10100 views
Discussion

Generating data in csv format from netlist simulation

Category: Custom IC Design

By sidm
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updated over 4 years ago by Andrew Beckett

3 replies • 10671 views
Discussion

2 Tone VerilogA signal source does not work in Harmonic balance

Category: Custom IC Design

By ChristophHoehn
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updated over 4 years ago by Andrew Beckett

3 replies • 10504 views
Discussion

lxSeriesTerms for a 4-port device

Category: Custom IC Design

By FormerMember
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updated over 4 years ago by Andrew Beckett

1 replies • 4182 views
Discussion

Accessing simulation variables in verilog-a without passed parameter?

Category: Custom IC Design

By MikeVP
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updated over 4 years ago by Andrew Beckett

3 replies • 12634 views
Discussion

passing a result from previous test ADEXL

Category: Custom IC Design

By stefan111
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updated over 4 years ago by stefan111

2 replies • 12690 views
Discussion

How to plot using Simulation files stored in a folder?

Category: Custom IC Design

By Shashank M Rao
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updated over 4 years ago by Andrew Beckett

2 replies • 10411 views
Discussion

Trying to make a custom bindkey for Virtuoso to work - Select by line but for certain object types only

Category: Custom IC Design

By Tom Sawyer
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updated over 4 years ago by Tom Sawyer

2 replies • 1864 views

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