Custom IC Design

Latest Posts

Discussion

Update global variables from active setup to run plan

Category: Custom IC Design

By rod1
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updated over 4 years ago by rod1

3 replies • 12218 views
Discussion

Run plan for running a single test with different variables each time

Category: Custom IC Design

By Ernesto1
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updated over 4 years ago by rod1

3 replies • 12247 views
Discussion

Copied adexl view have a reference to original view's history paths in data.sdb

Category: Custom IC Design

By PatrikOsgnach
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updated over 4 years ago by Danielrayray

6 replies • 3922 views
Discussion

make smaller or hide overlay in Cadence Layout XL

Category: Custom IC Design

By hesdeadJim
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updated over 4 years ago by Andrew Beckett

1 replies • 10443 views
Discussion

NPORT compression "not working"

Category: Custom IC Design

By TommasoF
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updated over 4 years ago by TommasoF

5 replies • 2863 views
Discussion

Terminal is inherited in switch master XXX and not inherited in place master YYY

Category: Custom IC Design

By jjwikner
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updated over 4 years ago by Andrew Beckett

4 replies • 12680 views
Discussion

Resistor Noise Calculation using FFT and Noise Analysis is different

Category: Custom IC Design

By Nader Fathy
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updated over 4 years ago by FormerMember

7 replies • 16228 views
Discussion

Issues in accuracy of clock generation in Verilog-AMS with white noise jitter

Category: Custom IC Design

By RFStuff
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updated over 4 years ago by RFStuff

10 replies • 16564 views
Discussion

How do I set transient strobeoutput to "all" in AMS simulation?

Category: Custom IC Design

By Nader Fathy
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updated over 4 years ago by Nader Fathy

2 replies • 1592 views
Discussion

How to plot the difference of simulation result from Monte carlo and standard simulation?

Category: Custom IC Design

By Martinsh
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updated over 4 years ago by Andrew Beckett

9 replies • 14266 views
Discussion

VIVA zoom horizontal/vertical

Category: Custom IC Design

By amacSS
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updated over 4 years ago by amacSS

2 replies • 1705 views
Discussion

Bad value "primary" for parameter - Characterising cells using Liberate

Category: Custom IC Design

By iamKarthikBK
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started over 4 years ago

0 replies • 1362 views
Discussion

import a Spice Model in a schematic

Category: Custom IC Design

By Friedrich
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updated over 4 years ago by Friedrich

3 replies • 22206 views
Discussion

Connecting PMOS body to VSS! in Layout XL

Category: Custom IC Design

By Demi
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updated over 4 years ago by Quek

1 replies • 19104 views
Discussion

"the following branches form a loop of rigid branches"

Category: Custom IC Design

By Jose Sarmento
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updated over 4 years ago by Jose Sarmento

2 replies • 3264 views

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