Custom IC Design

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Hierarchical Parasitic Extraction & Cadence Tools

Category: Custom IC Design

By jimito13

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updated over 12 years ago by GabrielB

24 replies • 19401 views
Discussion

How do I re-load the .cadence directory via SKILL w/o restarting a session?

Category: Custom IC Design

By Julia

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updated over 12 years ago by Julia

4 replies • 1903 views
Discussion

How to write the expression for two currents' signal and plot them with Temperature

Category: Custom IC Design

By bhl3302

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updated over 12 years ago by bhl3302

2 replies • 7594 views
Discussion

problem: W and L of a transistor not shown in edit-> object-> properties

Category: Custom IC Design

By apple419

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updated over 12 years ago by beny

3 replies • 2340 views
Discussion

Histograms not showing in MC Analysis

Category: Custom IC Design

By Flyyn Rider

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updated over 12 years ago by Flyyn Rider

1 replies • 13995 views
Discussion

Regarding Smoothness in transient analysis

Category: Custom IC Design

By RFStuff

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updated over 12 years ago by Andrew Beckett

6 replies • 16705 views
Discussion

Layout pin problem: net name distributes via transistor

Category: Custom IC Design

By jeffreyprin

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started over 12 years ago

0 replies • 14699 views
Discussion

Is there a way in Verilog-A to know if transient noise analysis is run?

Category: Custom IC Design

By SharksFan

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updated over 12 years ago by Andrew Beckett

3 replies • 15582 views
Discussion

switching between spectre and mmsim

Category: Custom IC Design

By NcfC

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updated over 12 years ago by NcfC

4 replies • 16045 views
Discussion

axlExportOutputView creates an empty file

Category: Custom IC Design

By adeuser777

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updated over 12 years ago by Andrew Beckett

1 replies • 13982 views
Discussion

converting verilog to SPICE netlist

Category: Custom IC Design

By govind2306

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updated over 12 years ago by Andrew Beckett

1 replies • 21021 views
Discussion

Error in MMSIM when executing on 64bit machine

Category: Custom IC Design

By Arslan

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updated over 12 years ago by Andrew Beckett

1 replies • 14372 views
Discussion

Spectre adexl results to sdb/pcf file?

Category: Custom IC Design

By DeepG

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started over 12 years ago

0 replies • 838 views
Discussion

Abstract Generation Crashes during Step pins in a given cell

Category: Custom IC Design

By jorenrefuerzo

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updated over 12 years ago by ColinSutlieff

1 replies • 13763 views
Discussion

Solving a differential equation using VerilogA Model

Category: Custom IC Design

By RFStuff

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started over 12 years ago

0 replies • 14754 views

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