Custom IC Design

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Discussion

Exporting the waveforms from Cadence ADE to plot it in Mathlab

Category: Custom IC Design

By NorNand

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updated over 6 years ago by NorNand

2 replies • 15459 views
Discussion

It seems auCdlPutMathExprInSingleQuotes only works for subckt netlister(like ansCdlSubcktCall and ansCdlSubcktCallExtended) not for instance netlister(like ansCdlHnlPrintInst). Is it possible to make it happen too?

Category: Custom IC Design

By zssfred

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updated over 6 years ago by zssfred

4 replies • 1414 views
Discussion

what is the difference between "parseAsCEL no" and "parseAsCEL don't use"?

Category: Custom IC Design

By zssfred

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updated over 6 years ago by zssfred

4 replies • 2310 views
Discussion

Virtuoso 6.1.8 plotted expressions in VIVA do not fit to evaluated expressions in assembler

Category: Custom IC Design

By Michael H

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updated over 6 years ago by Michael H

2 replies • 15113 views
Discussion

Library manager shows layout cell is checked out BUT there are no lock files in the directory path.

Category: Custom IC Design

By MGoodlett

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updated over 6 years ago by Andrew Beckett

1 replies • 17127 views
Discussion

launching ModGen in Cadence virtuoso Layout editor

Category: Custom IC Design

By NorNand

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updated over 6 years ago by Andrew Beckett

1 replies • 14713 views
Discussion

Which virtuoso version is more recent, IC 6.1.7-64b or IC 6.1.7.500.17 ?

Category: Custom IC Design

By Marben

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updated over 6 years ago by Marben

6 replies • 19677 views
Discussion

icfb (Ver. 5.1.0) failed to start with openLDAP authentication enabled

Category: Custom IC Design

By rfvlsilab

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updated over 6 years ago by pyohayo

11 replies • 20540 views
Discussion

Terminal in CDF termOder is invalid (CDL netlist)

Category: Custom IC Design

By PatrikOsgnach

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updated over 6 years ago by PatrikOsgnach

6 replies • 18042 views
Discussion

Parameterizing model section

Category: Custom IC Design

By NickA

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updated over 6 years ago by Andrew Beckett

1 replies • 13542 views
Discussion

Is there any shortcut, bindkey to bring up CIW window quickly?

Category: Custom IC Design

By BaaB

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updated over 6 years ago by Andrew Beckett

5 replies • 15210 views
Discussion

License wait limit for schematic netlisting commands

Category: Custom IC Design

By MOSFET

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updated over 6 years ago by Andrew Beckett

1 replies • 13892 views
Discussion

Simulation crashed - Killed by user

Category: Custom IC Design

By BaaB

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updated over 6 years ago by Dimitra Papazoglou

5 replies • 4196 views
Discussion

Direct Plot then Transient Signal stop updating after some time

Category: Custom IC Design

By BaaB

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updated over 6 years ago by Andrew Beckett

5 replies • 15925 views
Discussion

how to pass array of parameters through CDF down to a verilogA code?

Category: Custom IC Design

By naderi

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updated over 6 years ago by Andrew Beckett

11 replies • 23735 views

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