Custom IC Design

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Discussion

Post-layout simulation without spectre view in transistor cell

Category: Custom IC Design

By Javadgo
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updated over 1 year ago by Javadgo

6 replies • 5637 views
Discussion

ADE including a simulation file with a relative path

Category: Custom IC Design

By Huf
•
started over 1 year ago

0 replies • 3979 views
Discussion

ADE (Explorer / Assembler) Stimuli Assignment as a floating voltage source

Category: Custom IC Design

By Huf
•
started over 1 year ago

0 replies • 3753 views
Discussion

Can't unlock explorer run on ADE Assembler

Category: Custom IC Design

By Thais
•
updated over 1 year ago by Andrew Beckett

1 replies • 1321 views
Discussion

Is it possible to setup Layout GXL to use multiple CPU cores?

Category: Custom IC Design

By RuihW
•
started over 1 year ago

0 replies • 3829 views
Discussion

VPULSE PARAMETERS INDICATION ??

Category: Custom IC Design

By ganesh9989
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updated over 1 year ago by Andrew Beckett

1 replies • 4635 views
Discussion

Change setup of the extracted netlist (Calibre view) -- extraction with QRC

Category: Custom IC Design

By BitanMallik
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started over 1 year ago

0 replies • 629 views
Discussion

LEF generated with non-used layer info

Category: Custom IC Design

By RuihW
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started over 1 year ago

0 replies • 3897 views
Discussion

Assembler Global Optimization

Category: Custom IC Design

By sram17
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updated over 1 year ago by sram17

1 replies • 4174 views
Discussion

Device Check Asserts that only apply within a specific time window

Category: Custom IC Design

By dconnern33
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started over 1 year ago

0 replies • 4243 views
Discussion

input-referred noise measurement issue

Category: Custom IC Design

By engmsalik321
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updated over 1 year ago by Andrew Beckett

4 replies • 6628 views
Discussion

ASU 7nm installation in Cadence Virtuoso

Category: Custom IC Design

By samanway
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updated over 1 year ago by Andrew Beckett

1 replies • 4257 views
Discussion

how to write log while using features of Advanced Optimization ?

Category: Custom IC Design

By Monarch03116
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updated over 1 year ago by Andrew Beckett

1 replies • 3905 views
Discussion

Parametric Analysis Maestro

Category: Custom IC Design

By AghilesD
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updated over 1 year ago by Frank Wiedmann

1 replies • 5114 views
Discussion

Mapping the net names of schematic netlist and layout netlist

Category: Custom IC Design

By DEEPWATER
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updated over 1 year ago by Shawn Daniel Rodrigues

2 replies • 5224 views

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