Custom IC Design

Latest Posts

Discussion

Any option in VLS to save one particular layer in hierarchy to a new view?

Category: Custom IC Design

By ssram

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updated over 3 years ago by Andrew Beckett

3 replies • 13764 views
Discussion

Accuracy of CROSS() function in Verilog-A

Category: Custom IC Design

By RFStuff

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updated over 3 years ago by atulkumar245

8 replies • 26682 views
Discussion

Creating a New PCELL from an existing Pcell and adding A new parameter to it

Category: Custom IC Design

By RFStuff

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updated over 3 years ago by Andrew Beckett

3 replies • 15470 views
Discussion

Creating a string expression in ADEL (or explorer) output section

Category: Custom IC Design

By Svilen64

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updated over 3 years ago by Svilen64

6 replies • 12527 views
Discussion

Non-default path to 'si.env' configuration file when calling 'si' executable from the command line to export CDL netlist from OA schematic ?

Category: Custom IC Design

By lpacher

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updated over 3 years ago by Andrew Beckett

1 replies • 1798 views
Discussion

Simulation files for Circuit Optimization App Note

Category: Custom IC Design

By delgsy

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updated over 3 years ago by Andrew Beckett

1 replies • 8711 views
Discussion

How to inspect older Assembler test setups e.g. regarding tran analysis details?

Category: Custom IC Design

By StephanWeber

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updated over 3 years ago by Andrew Beckett

1 replies • 8691 views
Discussion

Applying multi-bit VCSV files in analog virtuoso schematic

Category: Custom IC Design

By Johanny Saenz

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updated over 3 years ago by Andrew Beckett

1 replies • 9604 views
Discussion

geomOr vs. geomCat

Category: Custom IC Design

By marcelpreda

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updated over 3 years ago by Andrew Beckett

1 replies • 8811 views
Discussion

Verilog A compact modeling

Category: Custom IC Design

By atulkumar245

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started over 3 years ago

0 replies • 8626 views
Discussion

simulation not running when starting a new test simulation

Category: Custom IC Design

By dileeps

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started over 3 years ago

0 replies • 9711 views
Discussion

How to measure dynamic power consumption and static power consumption separately

Category: Custom IC Design

By Holz

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updated over 3 years ago by FormerMember

3 replies • 18741 views
Discussion

Cadence tool to analyse across-chip variations (distance-dependent mismatch)?

Category: Custom IC Design

By StephanWeber

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updated over 3 years ago by StephanWeber

2 replies • 9412 views
Discussion

missing information of OCEAN created from ADE

Category: Custom IC Design

By Oliver LZD

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started over 3 years ago

0 replies • 8254 views
Discussion

input.scs generated from OCEAN removed some pxf analysis options

Category: Custom IC Design

By QUBOZHOU

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updated over 3 years ago by Oliver LZD

1 replies • 13323 views

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