Custom IC Design

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Discussion

Virtuoso 6.1.8 plotted expressions in VIVA do not fit to evaluated expressions in assembler

Category: Custom IC Design

By Michael H

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updated over 6 years ago by Michael H

2 replies • 14738 views
Discussion

Library manager shows layout cell is checked out BUT there are no lock files in the directory path.

Category: Custom IC Design

By MGoodlett

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updated over 6 years ago by Andrew Beckett

1 replies • 16651 views
Discussion

launching ModGen in Cadence virtuoso Layout editor

Category: Custom IC Design

By NorNand

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updated over 6 years ago by Andrew Beckett

1 replies • 14394 views
Discussion

Which virtuoso version is more recent, IC 6.1.7-64b or IC 6.1.7.500.17 ?

Category: Custom IC Design

By Marben

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updated over 6 years ago by Marben

6 replies • 19071 views
Discussion

icfb (Ver. 5.1.0) failed to start with openLDAP authentication enabled

Category: Custom IC Design

By rfvlsilab

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updated over 6 years ago by pyohayo

11 replies • 20026 views
Discussion

Terminal in CDF termOder is invalid (CDL netlist)

Category: Custom IC Design

By PatrikOsgnach

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updated over 6 years ago by PatrikOsgnach

6 replies • 17552 views
Discussion

Parameterizing model section

Category: Custom IC Design

By NickA

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updated over 6 years ago by Andrew Beckett

1 replies • 13231 views
Discussion

Is there any shortcut, bindkey to bring up CIW window quickly?

Category: Custom IC Design

By BaaB

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updated over 6 years ago by Andrew Beckett

5 replies • 14829 views
Discussion

License wait limit for schematic netlisting commands

Category: Custom IC Design

By MOSFET

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updated over 6 years ago by Andrew Beckett

1 replies • 13586 views
Discussion

Simulation crashed - Killed by user

Category: Custom IC Design

By BaaB

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updated over 6 years ago by Dimitra Papazoglou

5 replies • 4009 views
Discussion

Direct Plot then Transient Signal stop updating after some time

Category: Custom IC Design

By BaaB

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updated over 6 years ago by Andrew Beckett

5 replies • 15536 views
Discussion

how to pass array of parameters through CDF down to a verilogA code?

Category: Custom IC Design

By naderi

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updated over 6 years ago by Andrew Beckett

11 replies • 23178 views
Discussion

Limited History Entries?

Category: Custom IC Design

By tabreu

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updated over 6 years ago by Andrew Beckett

1 replies • 15480 views
Discussion

Cannot extract spectre transient simulation data using Matlab

Category: Custom IC Design

By peter6g

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updated over 6 years ago by peter6g

7 replies • 16097 views
Discussion

ADE-XL Simulation Lost After Cadence Crash

Category: Custom IC Design

By armenhr

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updated over 6 years ago by Andrew Beckett

4 replies • 16319 views

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