Custom IC Design

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Discussion

Navigator net highlight/probe and navigator net 'XL status' issue

Category: Custom IC Design

By 94d33m

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started over 4 years ago

0 replies • 1584 views
Discussion

Selecting shapes contained in/inside shape

Category: Custom IC Design

By ajk68

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updated over 4 years ago by ajk68

3 replies • 1918 views
Discussion

Regarding cadence virtuoso installation

Category: Custom IC Design

By Simhadri

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updated over 4 years ago by Andrew Beckett

1 replies • 11571 views
Discussion

[Virtuoso layout XL] How to switch between quick align User Spacing and quick align No Spacing with single keystroke?

Category: Custom IC Design

By 94d33m

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updated over 4 years ago by Andrew Beckett

3 replies • 16863 views
Discussion

How to run encrypted Pspice model in Cadence?

Category: Custom IC Design

By Firdos

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updated over 4 years ago by Frank Wiedmann

1 replies • 11025 views
Discussion

Relative path for Ocean script in Maestro

Category: Custom IC Design

By FormerMember

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updated over 4 years ago by FormerMember

1 replies • 5190 views
Discussion

skipping digital registers in analog extracted simulations

Category: Custom IC Design

By Mohamayreh

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updated over 4 years ago by FormerMember

1 replies • 9459 views
Discussion

How to keep attached shapes of a multipart path when chopping the multipart path

Category: Custom IC Design

By Strongy2021

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started over 4 years ago

0 replies • 9237 views
Discussion

Simulation of gate leakage current using cadence

Category: Custom IC Design

By Minghao

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updated over 4 years ago by FormerMember

3 replies • 13251 views
Discussion

Frequency Measurement when clock is constant (veriloga)

Category: Custom IC Design

By ElZorro

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started over 4 years ago

0 replies • 10497 views
Discussion

Double sided spectrum in PSS simulation

Category: Custom IC Design

By Alok110

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updated over 4 years ago by Alok110

3 replies • 10902 views
Discussion

How to snap different layers to the edges of other layers? (Virtuoso Layout XL)

Category: Custom IC Design

By 94d33m

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started over 4 years ago

0 replies • 11007 views
Discussion

Generating Layout - pcellEvalFailed

Category: Custom IC Design

By nokta

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updated over 4 years ago by Andrew Beckett

6 replies • 4673 views
Discussion

EMIR simulation fails with EMIR-1099 code

Category: Custom IC Design

By ZMOS

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started over 4 years ago

0 replies • 10015 views
Discussion

Library charecterization without post-layout netlists

Category: Custom IC Design

By iamKarthikBK

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updated over 4 years ago by iamKarthikBK

15 replies • 14588 views

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