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Custom IC Design

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  • Discussion

    how to draw using y vs y?

    Category: Custom IC Design

    By SGGS

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    updated over 6 years ago by Candido

    2 replies • 20541 views
  • Discussion

    Phase Noise simulation accuracy

    Category: Custom IC Design

    By Gmacera

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    •

    updated over 6 years ago by Frank Wiedmann

    1 replies • 13480 views
  • Discussion

    Cadence Liberate for characterizing

    Category: Custom IC Design

    By fengye

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    •

    updated over 6 years ago by fengye

    8 replies • 17114 views
  • Discussion

    LVS: Calibre Missing Instance

    Category: Custom IC Design

    By wgtkan

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    •

    updated over 6 years ago by wgtkan

    2 replies • 18558 views
  • Discussion

    Is there a way to customize the netlist fom subckt netlister(like ansCdlSubcktCall and ansCdlSubcktCallExtended)?

    Category: Custom IC Design

    By zssfred

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    •

    updated over 6 years ago by zssfred

    6 replies • 2039 views
  • Discussion

    Exporting the waveforms from Cadence ADE to plot it in Mathlab

    Category: Custom IC Design

    By NorNand

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    •

    updated over 6 years ago by NorNand

    2 replies • 15187 views
  • Discussion

    It seems auCdlPutMathExprInSingleQuotes only works for subckt netlister(like ansCdlSubcktCall and ansCdlSubcktCallExtended) not for instance netlister(like ansCdlHnlPrintInst). Is it possible to make it happen too?

    Category: Custom IC Design

    By zssfred

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    •

    updated over 6 years ago by zssfred

    4 replies • 1351 views
  • Discussion

    what is the difference between "parseAsCEL no" and "parseAsCEL don't use"?

    Category: Custom IC Design

    By zssfred

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    •

    updated over 6 years ago by zssfred

    4 replies • 2216 views
  • Discussion

    Virtuoso 6.1.8 plotted expressions in VIVA do not fit to evaluated expressions in assembler

    Category: Custom IC Design

    By Michael H

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    updated over 6 years ago by Michael H

    2 replies • 14862 views
  • Discussion

    Library manager shows layout cell is checked out BUT there are no lock files in the directory path.

    Category: Custom IC Design

    By MGoodlett

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    updated over 6 years ago by Andrew Beckett

    1 replies • 16800 views
  • Discussion

    launching ModGen in Cadence virtuoso Layout editor

    Category: Custom IC Design

    By NorNand

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    •

    updated over 6 years ago by Andrew Beckett

    1 replies • 14499 views
  • Discussion

    Which virtuoso version is more recent, IC 6.1.7-64b or IC 6.1.7.500.17 ?

    Category: Custom IC Design

    By Marben

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    updated over 6 years ago by Marben

    6 replies • 19264 views
  • Discussion

    icfb (Ver. 5.1.0) failed to start with openLDAP authentication enabled

    Category: Custom IC Design

    By rfvlsilab

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    •

    updated over 6 years ago by pyohayo

    11 replies • 20191 views
  • Discussion

    Terminal in CDF termOder is invalid (CDL netlist)

    Category: Custom IC Design

    By PatrikOsgnach

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    •

    updated over 6 years ago by PatrikOsgnach

    6 replies • 17711 views
  • Discussion

    Parameterizing model section

    Category: Custom IC Design

    By NickA

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    •

    updated over 6 years ago by Andrew Beckett

    1 replies • 13329 views
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