Custom IC Design

Latest Posts

Discussion

Which cadence's tool supports MEMS design?

Category: Custom IC Design

By south888888

$usertype
•
updated over 12 years ago by south888888

2 replies • 1268 views
Discussion

ADE window Freezes in IC5.141USR5

Category: Custom IC Design

By behrooz

$usertype
•
updated over 12 years ago by likelike

3 replies • 14419 views
Discussion

How to blackbox a device with spetial condition in Assura LVS

Category: Custom IC Design

By shushanik

$usertype
•
started over 12 years ago

0 replies • 13125 views
Discussion

Re: How do I call "load /path/usr/test.il" using bindkeys?

Category: Custom IC Design

By Rahim Abdulla

$usertype
•
updated over 12 years ago by Deepon Saha

3 replies • 2833 views
Discussion

Measurement of current in rcx extracted simulation

Category: Custom IC Design

By ankurprg

$usertype
•
updated over 12 years ago by ankurprg

4 replies • 14107 views
Discussion

help with non-existent pin

Category: Custom IC Design

By linbo

$usertype
•
updated over 12 years ago by Eduard Raines

2 replies • 17529 views
Discussion

Documentation about Connect Modules

Category: Custom IC Design

By freitas

$usertype
•
updated over 12 years ago by Quek

1 replies • 13554 views
Discussion

Equivalent of "aMarker", "bMarker" and "delta marker" of ViVA in SKILL?

Category: Custom IC Design

By Reinice

$usertype
•
updated over 12 years ago by Andrew Beckett

1 replies • 793 views
Discussion

OS to run cadence license manager

Category: Custom IC Design

By wighou

$usertype
•
updated over 12 years ago by wighou

5 replies • 15797 views
Discussion

Assura: Include other files

Category: Custom IC Design

By PekkaH

$usertype
•
updated over 12 years ago by PekkaH

2 replies • 13688 views
Discussion

Spectre simulation error

Category: Custom IC Design

By CCH01

$usertype
•
updated over 12 years ago by KD353

8 replies • 18661 views
Discussion

ViVA colors customization

Category: Custom IC Design

By dalistoj

$usertype
•
updated over 12 years ago by Andrew Beckett

1 replies • 13813 views
Discussion

.cdl file - getting the TX length and width

Category: Custom IC Design

By cadence4help

$usertype
•
updated over 12 years ago by skillUser

1 replies • 841 views
Discussion

Method to control subcircuit order when generating a Spectre netlist?

Category: Custom IC Design

By FormerMember

$usertype
•
updated over 12 years ago by FormerMember

2 replies • 7089 views
Discussion

simulating hierarchical VHDL design using AMS

Category: Custom IC Design

By Hesham2012

$usertype
•
updated over 12 years ago by Hesham2012

2 replies • 15516 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.