Custom IC Design

Latest Posts

Discussion

CDF simulation parameters do not update accordingly?

Category: Custom IC Design

By SUEE

$usertype
•
updated over 13 years ago by Andrew Beckett

7 replies • 19587 views
Discussion

Bindkey : P (Create Path) , somehow it doesn't work .

Category: Custom IC Design

By Charley Chen

$usertype
•
updated over 13 years ago by Charley Chen

2 replies • 892 views
Discussion

Tip of the Week: Use infotimes to define trans op point saves

Category: Custom IC Design

By archive

$usertype
•
updated over 13 years ago by Andrew Beckett

3 replies • 13793 views
Discussion

Bindkeys in IC 6.1.5

Category: Custom IC Design

By AlexGolberg

$usertype
•
updated over 13 years ago by AlexGolberg

2 replies • 13063 views
Discussion

Questions in stream out the layers used in a layout that includes three chips

Category: Custom IC Design

By SUEE

$usertype
•
updated over 13 years ago by Andrew Beckett

3 replies • 14966 views
Discussion

off grid polygons in Virtuoso

Category: Custom IC Design

By Darin Bell

$usertype
•
updated over 13 years ago by Quek

1 replies • 17454 views
Discussion

Intrinsic Capacitance

Category: Custom IC Design

By Cooktime

$usertype
•
updated over 13 years ago by Andrew Beckett

1 replies • 14093 views
Discussion

installscape can't find the right directory

Category: Custom IC Design

By FedericoPI

$usertype
•
updated over 13 years ago by Andrew Beckett

1 replies • 3141 views
Discussion

Assura QRC Back Annotation Question

Category: Custom IC Design

By jimstuy

$usertype
•
updated over 13 years ago by Quek

1 replies • 13477 views
Discussion

Help me with the trans/dc options.

Category: Custom IC Design

By Muffassir

$usertype
•
updated over 13 years ago by Muffassir

2 replies • 2094 views
Discussion

ADEXL (IC615) Output Intermittently Isn't Calculated

Category: Custom IC Design

By aakhavan

$usertype
•
updated over 13 years ago by Andrew Beckett

5 replies • 1514 views
Discussion

ocean script with added analysis for monte carlo

Category: Custom IC Design

By frogconsultant

$usertype
•
updated over 13 years ago by Andrew Beckett

1 replies • 13086 views
Discussion

Assura LVS - How to force shorted layout devices to be netlisted and compared?

Category: Custom IC Design

By miketqs

$usertype
•
updated over 13 years ago by Quek

3 replies • 2899 views
Discussion

doubts in layout devices

Category: Custom IC Design

By venuuuuu

$usertype
•
updated over 13 years ago by Quek

1 replies • 13142 views
Discussion

QRC Extraction Error (FLTTDTA-109002)

Category: Custom IC Design

By jaw500

$usertype
•
updated over 13 years ago by jaw500

4 replies • 14092 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.