Custom IC Design

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Discussion

Not able add pins to symbol; restricted by string length

Category: Custom IC Design

By ajmr

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updated over 4 years ago by ajmr

4 replies • 10737 views
Discussion

Greyed menu: "Run Assura Quantus QRC..." and "Run Assura Quantus QRC..."

Category: Custom IC Design

By manudupouy

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updated over 4 years ago by WenhaoY

35 replies • 23975 views
Discussion

Convert Digital Bus to an Integer value - Calculator Viva

Category: Custom IC Design

By FAwqati

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updated over 4 years ago by abdurrahman0234

10 replies • 19865 views
Discussion

Reduce the spacing between metals while placing stack auto via.

Category: Custom IC Design

By skillEater

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updated over 4 years ago by chanho

7 replies • 16782 views
Discussion

ViVA Customization using .cdsinit

Category: Custom IC Design

By hoodskier

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updated over 4 years ago by Andrew Beckett

10 replies • 21751 views
Discussion

Getting data from an "intersect"

Category: Custom IC Design

By CSCNalu

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updated over 4 years ago by FormerMember

6 replies • 4056 views
Discussion

if statement in ade xl

Category: Custom IC Design

By Holz

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updated over 4 years ago by Holz

3 replies • 16086 views
Discussion

Can I start a simulation in the mid night?

Category: Custom IC Design

By ichiro

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updated over 4 years ago by Andrew Beckett

1 replies • 10106 views
Discussion

ADE XL Not including Spectre Models

Category: Custom IC Design

By Zachary Nelson

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updated over 4 years ago by Andrew Beckett

5 replies • 11479 views
Discussion

I had an error of "matrix is singular" only by APS.

Category: Custom IC Design

By ichiro

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updated over 4 years ago by ichiro

2 replies • 1548 views
Discussion

Question about AC simulation with verilog-A model

Category: Custom IC Design

By dskang

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updated over 4 years ago by dskang

1 replies • 10751 views
Discussion

AGPDK cds_ff_mpt_v_1.0

Category: Custom IC Design

By Vamshi S K

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updated over 4 years ago by Andrew Beckett

1 replies • 10458 views
Discussion

Generating .lib file for synthesis using Genus from transistor level cells using Virtuoso

Category: Custom IC Design

By iamKarthikBK

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updated over 4 years ago by Guangjun Cao

28 replies • 31500 views
Discussion

compare two netlists

Category: Custom IC Design

By sjwprcker

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updated over 4 years ago by MaximX

3 replies • 15231 views
Discussion

Assura doesn't recognise pins generated from sources

Category: Custom IC Design

By iamKarthikBK

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updated over 4 years ago by iamKarthikBK

5 replies • 2776 views

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