Custom IC Design

Latest Posts

Discussion

Change code in veriloga view from external program

Category: Custom IC Design

By mikewu999
•
updated 10 months ago by Andrew Beckett

1 replies • 2401 views
Discussion

Verilog-A: Can I ignore WARNING (VACOMP-1047)

Category: Custom IC Design

By mikewu999
•
updated 10 months ago by Andrew Beckett

1 replies • 2575 views
Discussion

Transient Simulation waveform abnormal

Category: Custom IC Design

By SkkyLee
•
updated 10 months ago by hayess

1 replies • 2456 views
Discussion

Xcelium/Simvision/xrun running very slow (waiting for SimVision/Verisium Debug to connect...)

Category: Custom IC Design

By MT202407295352
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started 10 months ago

0 replies • 900 views
Discussion

How to use PSpice library in Virtuoso/Spectre?

Category: Custom IC Design

By Jason Lee
•
started 10 months ago

0 replies • 449 views
Discussion

How can I place stacked vias with the size exact same cut width without metals around?

Category: Custom IC Design

By TzuYun Chang
•
updated 10 months ago by TzuYun Chang

2 replies • 2578 views
Discussion

Config sweep View in Tests

Category: Custom IC Design

By Mooh
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started 10 months ago

0 replies • 2173 views
Discussion

Cannot access individual noise contributions using SpectreMDL

Category: Custom IC Design

By Carmi
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started 10 months ago

0 replies • 2037 views
Discussion

New CDF creation and callback

Category: Custom IC Design

By IM202410225248
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started 10 months ago

0 replies • 2195 views
Discussion

spectre 241 vs 211

Category: Custom IC Design

By kenc184
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updated 10 months ago by kenc184

2 replies • 2863 views
Discussion

A problem with setup when Monte Carlo simulation starts

Category: Custom IC Design

By Mdad
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started 10 months ago

0 replies • 2234 views
Discussion

Import LEF file failed due to layermap

Category: Custom IC Design

By TzuYun Chang
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started 10 months ago

0 replies • 2530 views
Discussion

Netlisting error when doing parametric sweep on transient simulation

Category: Custom IC Design

By Volker T
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updated 10 months ago by Volker T

1 replies • 2791 views
Discussion

How to Set Checks/Asserts as Default View After Simulation in Virtuoso Assembler

Category: Custom IC Design

By baltaci
•
updated 10 months ago by baltaci

4 replies • 1131 views
Discussion

Recommended delimiter in DSPF for deep probing

Category: Custom IC Design

By unSkilled
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updated 10 months ago by unSkilled

2 replies • 2913 views

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