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Custom IC Design

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  • Discussion

    Geometric wire options (VLE)

    Category: Custom IC Design

    By sPoK

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    updated over 12 years ago by sPoK

    4 replies • 14714 views
  • Discussion

    Is there a way to recover an adexl view that's missing its data.sdb file?

    Category: Custom IC Design

    By 123deepa

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    updated over 12 years ago by Andrew Beckett

    1 replies • 2682 views
  • Discussion

    Virtuoso Envlp Analysis Problem with Thermometer Waveform as Input

    Category: Custom IC Design

    By Richard85

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    started over 12 years ago

    0 replies • 13032 views
  • Discussion

    Query in Naming in schematic and layout

    Category: Custom IC Design

    By BB11

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    updated over 12 years ago by BB11

    2 replies • 13245 views
  • Discussion

    Design variables in FFT and THD measures

    Category: Custom IC Design

    By baenischfau

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    updated over 12 years ago by baenischfau

    4 replies • 14978 views
  • Discussion

    Corner Simulation

    Category: Custom IC Design

    By YonYon

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    updated over 12 years ago by Andrew Beckett

    1 replies • 14637 views
  • Discussion

    Assura DRC - round edges with geomSize() operation

    Category: Custom IC Design

    By PekkaH

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    updated over 12 years ago by Andrew Beckett

    1 replies • 872 views
  • Discussion

    Changing instance model by alter statement

    Category: Custom IC Design

    By ChrisEAS

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    updated over 12 years ago by Andrew Beckett

    3 replies • 14172 views
  • Discussion

    Regarding Transient analysis of Gate Charge

    Category: Custom IC Design

    By kapiljainwal

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    updated over 12 years ago by kapiljainwal

    2 replies • 13766 views
  • Discussion

    How to plot device parameters from transient sims.

    Category: Custom IC Design

    By archive

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    updated over 12 years ago by Andrew Beckett

    6 replies • 17919 views
  • Discussion

    Mixed Signal Simulation Question

    Category: Custom IC Design

    By brianzimmer

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    updated over 12 years ago by Andrew Beckett

    3 replies • 13729 views
  • Discussion

    OSS netlister: how to avoid netlisting of parameter "m"

    Category: Custom IC Design

    By Andreasm

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    started over 12 years ago

    0 replies • 716 views
  • Discussion

    verilog netlist to schematic

    Category: Custom IC Design

    By Myskill

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    updated over 12 years ago by Andrew Beckett

    3 replies • 15119 views
  • Discussion

    Manipulating a single Instance Iterations in Virtuoso

    Category: Custom IC Design

    By Battosai

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    updated over 12 years ago by Battosai

    5 replies • 18096 views
  • Discussion

    soi transistor

    Category: Custom IC Design

    By arundevnkumar

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    •

    updated over 12 years ago by Andrew Beckett

    3 replies • 13923 views
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